Role of test stress levels in detection of process-induced latent charging damage in MOS transistors

International Symposium on Plasma Process-Induced Damage, P2ID, Proceedings

Volumn , Issue , 1996, Pages 81-83

  Brozek, Tomasz ^a   Peng, Lihua ^a   Viswanathan, C R ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEGRADATION; ELECTRIC CHARGE; ELECTRONS; INTERFACES (MATERIALS); MOSFET DEVICES; PLASMA APPLICATIONS; STRESS ANALYSIS;

CHARGING DAMAGE; ELECTRON TRAP GENERATION; FOWLER-NORDHEIM STRESS TEST; STRESS LEVEL;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0029722816     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)