A low-cost solder-bumped chip scale package -NuCSP

Circuit World

Volumn 24, Issue 3, 1998, Pages 11-25

  Lau, John H ^a   Chang, Chris ^a   Chen, Tony ^a   Cheng, David ^a   Lao, Eric ^b  

^a Express Packaging Systems Inc   (United States)

^b Kwei Shan Ind Park   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; FLIP CHIP DEVICES; MICROPROCESSOR CHIPS; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; SOLDERING ALLOYS; SUBSTRATES; SURFACE MOUNT TECHNOLOGY;

CHIP SCALE PACKAGES (CSP); LAND GRID ARRAYS (LGA);

ELECTRONICS PACKAGING;

EID: 0032051229     PISSN: 03056120     EISSN: None     Source Type: Journal    
DOI: 10.1108/03056129810208429     Document Type: Article

References (30)

1. Lau, J.H. and Lee, R., Chip Scale Packages: Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, NY, 1998.
2. Lau, J.H., Wong, C.P., Prince, J.L. and Nakayama, W., Electronic Packaging: Design, Materials, Process, and Reliability, McGraw-Hill, New York, NY, 1998.
3. Lau, J.H. and Pao, Y.-H., Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, New York, NY, 1997.
4. Lau, J.H., Flip Chip Technologies, McGraw-Hill, New York, NY, 1996.
5. Lau, J.H., Ball Grid Technology, McGraw-Hill, New York, NY, 1995.
6. Lau, J.H., Chip on Board Technologies for Multichip Modules, Van Nostrand Reinhold, New York, NY, 1994.
7. Lau, J.H., Handbook of Fine Pitch Surface Mount Technology, Van Nostrand Reinhold, New York, NY, 1994.
8. Frear, D., Morgan, H., Burchett, S. and Lau, J., The Mechanics of Solder Alloy, Van Nostrand Reinhold, New York, NY, 1994.
9. Lau, J.H., Thermal Stress and Strain in Microelectronics Packaging, Van Nostrand Reinhold, New York, NY, 1993.
10. Lau, J.H., Handbook of Tape Automated Bonding, Van Nostrand Reinhold, New York, NY, 1992.
11. Lau, J.H., Solder Joint Reliability, Theory and Applications, Van Nostrand Reinhold, New York, NY, 1991.
12. Lau, J.H., "Electronics packaging technology update: BGA, CSP, DCA, and flip chip", Circuit World, Vol. 23 No. 4, June 1997, pp. 22-5.
13. Chou, T. and Lau, J.H., "A low-cost chip size package - NuCSP", Circuit World, Vol. 24 No. 1, November 1997, pp. 34-8.
14. Lau, J.H., "Solder joint reliability of a low-cost chip size package - NuCSP", Proceedings of ISHM Microelectronics Symposiums, October 1997, pp. 691-6.
15. Lau, J.H., Chang, C. and Chen, R., "Effects of underfill encapsulant on the mechanical and electrical performance of a functional flip chip device", Proceedings of the First IEEE International Symposium on Polymeric Electronics Packaging, October 1997, pp. 265-72.
16. Kasai, J., Sato, M., Fujisawa, T., Uno, T., Waki, M., Hayashida, K. and Kawahara, T., "Low-cost chip scale package for memory products", Proceedings of SMI Conference, August 1995, pp. 6-17.
17. Murakami, G., "Rationale for chip scale packaging (CSP) rather than multichip modules (MCM)", Proceedings of SMI Conference, August 1995, pp. 1-5.
18. Lee, S., Lee, J., Oh, S. and Chung, H., "Passivation cracking mechanism in high density memory devices assembled in SOJ packages adopting LOC die attach technique", Proceedings of IEEE Electronic Components & Technology Conference, May 1995, pp. 455-62.
19. Amagai, M., "The effect of stress intensity of package cracking in lead-on-chip (LOC) packages", Proceedings of IEEE Japan International Electronics Manufacturing Technology Symposium, December 1995, pp. 415-20.
20. Okugawa, Y., Yoshida, T., Suzuki, T. and Nakayoshi, H., "New tape LOC adhesive tapes", Proceedings of IEEE Electronic Components & Technology Conference, May 1994, pp. 570-4.
21. Nakayoshi, H., Izawa, N., Ishikawa, T. and Suzuki, T., "Memory package with LOC structure using new adhesive material", Proceedings of IEEE Electronic Components & Technology Conference, May 1994, pp. 575-9.
22. Kunitomo, Y., "Practical chip size package realized by ceramic LGA substrate and SBB technology", Proceedings of SMI Conference, August 1995, pp. 18-25.
23. Master, R., Jackson, R., Ray, S. and Ingraham, A., "Ceramic mini-ball grid array package for high speed device", Proceedings of IEEE Electronic Components & Technology Conference, May 1995, pp. 46-50.
24. Lall, P., Gold, G., Miles, B., Banerji, K., Thompson, P., Koehler, C. and Adhihetty, I., "Reliability characterization of the SLICC package", Proceedings of IEEE Electronic Components & Technology Conference, May 1996, pp. 1202-10.
25. Iwasaki, H.,"CSTP: chip scale thin package", Proceedings of SEMICON Japan, November 1994, pp. 488-95.
26. Forman, G., Fillion, R., Kole, R., Wojnarowski, R. and Rose, J., "Development of GE's plastic thin-zero outline package (TZOP) technology", Proceedings of IEEE Electronic Components & Technology Conference, May 1995, pp. 664-8.
27. Matsuda, S., Kata, K. and Hagimoto, E., "Simple-structure, generally applicable chip-scale package", Proceedings of IEEE Electronic Components & Technology Conference, May 1995, pp. 218-23.
28. Tanigawa, S., Igarashi, K., Nagasawa, M. and Yeti, N., "The resin molded chip size package (MCSP)", Proceedings of IEEE Japan International Electronics Manufacturing Technology Symposium, December 1995, pp. 410-15.
29. Kayo, T., Be, K., Sakaguchi, N. and Wakabayashi, S., "Reliability of mBG A mounted on a printed circuit board", Proceedings of SMI Conference, August 1995, pp. 43-56.
30. Yasunaga, M., Baba, S., Matsuo, M., Matsushima, H., Nako, S. and Tachikawa, T., "Chip scale package (CSP): a lightly dressed LSI chip", Proceedings of IEEE Japan International Electronics Manufacturing Technology Symposium, December 1994, pp. 169-76.