Practical algorithm for retiming level-clocked circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1996, Pages 440-445

  Maheshwari, Naresh ^a   Sapatnekar, Sachin S ^a  

^a IOWA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; ELECTRIC NETWORK SYNTHESIS; MATHEMATICAL MODELS; OPTIMIZATION; VLSI CIRCUITS;

LEVEL CLOCKED CIRCUITS; RETIMING;

TIMING CIRCUITS;

EID: 0030386860     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)