Controlling plasma charge damage in advanced semiconductor manufacturing-challenge of small feature size device, large chip size, and large wafer size

IEEE Transactions on Electron Devices

Volumn 45, Issue 3, 1998, Pages 722-730

  Aum, Paul K ^a,c   Brandshaft, Richard ^a   Brandshaft, Donald ^b   Dao, Thuy B ^a  

^a Spider Systems Inc   (United States)

^b IC Editors Inc   (United States)

^c MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SOFTWARE; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; MOSFET DEVICES; SEMICONDUCTOR DEVICE STRUCTURES; SILICON WAFERS; SUBSTRATES; ULSI CIRCUITS;

PLASMA CHARGE DAMAGE; SOFTWARE PACKAGE DESIGN RULE CHECK (DRC);

INTEGRATED CIRCUIT LAYOUT;

EID: 0032022707     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.661234     Document Type: Article

References (16)

1. M. Nakamura, K. Hashimoto, H. Mori, M. Koyanani, and P. Aum, Eds., Semiconductor Process Induced Charge Damage. Tokyo, Japan: Realize Inc., 1995 (in Japanese).
2. Proceedings of International Symposium on Plasma Process-Induced Damage. Sunnyvale, ÇA: AVS, 1996.
3. K. Mameno, H. Nagasawa, A. Nishida, and H. Fujiwara, "Ion-implantation-induced damage to gate oxide due to charge injection and ion bombardment," in Proc. Int. Symp. Plasma Process-Induced Damage, May 13-14, 1996, pp. 206-209.
4. T. Watanabe and Y. Yoshida, "Dielectric breakdown of gate insulator due to reactive ion etching," Solid State Technol., vol. 27, no. 4, pp. 263-268, Apr. 1984.
5. Y. Kawamoto, "MOS gate insulator breakdown caused by exposure to plasma," in Proc. Dry Process Symp., Inst. Elect. Eng., Oct. 1985, pp. 132-136.
6. K. Hashimoto, "New phenomena of charge damage in plasma etching: Heavy damage only through dense-line antenna," Jpn. J. Appl. Phys., vol. 32, pp. 6109-6112, 1993.
7. K. Hashimoto, Y. Hikosaka, A. Hasegawa, and M. Nakamura, "Reduction of electron shading damage by using synchronous bias in pulsed plasma," in Proc. Dry Process Symp., Inst. Elect. Eng., Nov. 1995, pp. 33-37.
8. H. Shin, K. Noguchi, X.-Y. Qian, N. Jha, G. Hill, and C. Hu, "Plasma etching charge-up damage to thin oxides," IEEE Electron Device Lett., vol. 14, pp. 88-90, Feb. 1993.
9. Kin P. Cheung and C. P. Chang, "Plasma-charging damage-A physical model," J. Appl. Phys., vol. 75, no. 9, pp. 4415-4419, 1994.
10. K. P. Cheung, "An efficient method for plasma-charging damage measurement," IEEE Electron Device Lett., vol. 15, pp. 460-462, Nov. 1994.
11. K. Cheung, D. Misra, K. Steiner, J. Colonell, C. Chang, W. Lai, C. Liu, R. Liu, and C. Pai, "Is n-MOSFET hot carrier lifetime degraded by charging damage?," in Proc. Int. Symp. Plasma Process-Induced Damage, May 13-14 1997, pp. 186-188.
12. T. Dao, "Charge damage evaluations using SPIDER test structures," in Semiconductor Process Induced Charge Damage. Tokyo, Japan: Realize Inc., 1995, pp. 156-169 (in Japanese).
13. Y. Heo, B. Park, and J. Lee, "The effect of guard line on plasma damage," in Proc. Int. Symp. Plasma Process-Induced Damage, May 13-14 1996, pp. 94-97.
14. B. Chapman, Glow Discharge Processes. New York: Wiley, 1980.
15. S. Sakamori, T. Maruyama, and N. Fujiwara, "Reduction of electron shading damage with pulse-modulated ECR plasma," in Proc. Int. Symp. Plasma Process-Induced Damage, May 13-14 1997, pp. 55-58.
16. G. Hwang and K. Giapis, "On the link between electron shadowing and charging damage," in Proc. Int. Symp. Plasma Process-Induced Damage, May 13-14 1997, pp. 63-66.