Diagnosis of clustered faults and wafer testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 2, 1998, Pages 136-148

  Huang, Kaiyuan ^a   Agarwal, Vinod K ^b   Thulasiraman, K ^c  

^a NORTEL NETWORKS   (Canada)

^b LV Software   (United States)

^c University of Oklahoma   (United States)

Author keywords

Boundary scan; Diagnosis; Fault clustering; Probabilistic diagnosis; Probeless testing; Vlsi testing; Wafer testing

Indexed keywords

ALGORITHMS; FAILURE ANALYSIS; PROBABILITY; SILICON WAFERS; VLSI CIRCUITS;

BOUNDARY SCAN; FAULT CLUSTERING; PROBABILISTIC DIAGNOSIS;

INTEGRATED CIRCUIT TESTING;

EID: 0032001495     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.681263     Document Type: Article

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