The Weighted Random Test-Pattern Generator

IEEE Transactions on Computers

Volumn C-24, Issue 7, 1975, Pages 695-700

  Schnurmann, H Daniel ^a   Lindbloom, Eric ^a   Carpenter, Robert G ^a  

^a IBM   (United States)

Author keywords

Fault detecting patterns; heuristic algorithm; large scale integration; test pattern generator; testing; testing algorithms; weighted random patterns

Indexed keywords

INTEGRATED CIRCUIT TESTING;

EID: 0016535251     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1975.224290     Document Type: Article

References (7)

1. W. G. Bouricius et al., “Algorithms for detection of faults in logic circuits,” IEEE Trans. Comput., vol. C-20, pp. 1258–1264, Nov. 1971.
2. J. P. Roth, “Diagnosis of automata failure: A calculus and a method,” IBM J. Res. Develop., vol. 10, no. 4, pp. 278–291, 1966.
3. G. R. Putzolu and J. P. Roth, “An algorithm and a program for generation of test patterns for sequential circuits,” in Proc. 3rd Hawaii Int. Conf. Syst. Sci., 1970, pp. 64–67.
4. D. W. Bray, “The ATVG program: A test vector generator for sequential networks,” in Conf. Rec., 2nd Workshop Fault Detection and Diagnosis, Lehigh Univ., Bethlehem, Pa., 1971, pp. 42–54.
5. R. G. Carpenter, E. Lindbloom, and T. M. McMahon, Jr., “Statistical logic test system having a weighted random test pattern generator,” U. S. Patent 3 719 885, Mar. 6, 1973.
6. S. W. Golomb, Shift Register Sequences. San Francisco: Holden-Day, 1967.
7. H. D. Schnurmann, “A computer program for weighted test pattern generation in Monte Carlo testing of integrated circuits,” IBM Tech. Disclosure Bull., vol. 16, pp. 417–423, July 1973.