Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 2, 1998, Pages 260-267

  Takashima, Daisaburo ^a,b,c,d   Oowaki, Yukihito ^a,e,f,g   Watanabe, Shigeyoshi ^a,h,i   Ohuchi, Kazunori ^a,d,j  

^a TOSHIBA CORPORATION   (Japan)

^b SOPHIA UNIVERSITY   (Japan)

^c Research and Development Center   (Japan)

^d Institute of Electronics   (Japan)

^e UNIVERSITY OF TOKYO   (Japan)

^f UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^g National Laboratory for High Energy Physics   (Japan)

^h KEIO UNIVERSITY   (Japan)

ⁱ TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^j TOHOKU UNIVERSITY   (Japan)

more..

Author keywords

CMOS integrated circuits; High speed bus; Interchip communication

Indexed keywords

LSI CIRCUITS; MICROPROCESSOR CHIPS; SCHEMATIC DIAGRAMS; SPURIOUS SIGNAL NOISE;

HIGH-SPEED BUS; INTERCHIP COMMUNICATION;

CMOS INTEGRATED CIRCUITS;

EID: 0031996753     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.658628     Document Type: Article

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