Noise suppression scheme for giga-scale DRAM with hundreds of I/Os

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1996, Pages 196-197

  Takashima, D ^a   Oowaki, Y ^a   Watanabe, S ^a   Ohuchi, K ^a   Matsunaga, J ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; ELECTRIC DISTORTION; INTERFERENCE SUPPRESSION; MULTIPLEXING EQUIPMENT; PRINTED CIRCUIT BOARDS; SPURIOUS SIGNAL NOISE; TRANSMISSION LINE THEORY;

CONSTANT CURRENT VOLTAGE DOWN CONVERTER; INDUCTANCE INDUCED VOLTAGE BOUNCES; NOISE REDUCTION EFFECT; SIMULATED WAVEFORMS;

RANDOM ACCESS STORAGE;

EID: 0029725232     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)