VLSI architectures for multiplication in GF(2m) for application tailored digital signal processors

IEEE Workshop on VLSI Signal Processing, Proceedings

Volumn , Issue , 1996, Pages 55-64

  Drescher, W ^a   Fettweis, G ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; DIGITAL SIGNAL PROCESSING; TECHNOLOGY; VLSI CIRCUITS;

FINITE FIELD ARITHMETIC;

MULTIPLYING CIRCUITS;

EID: 0030385756     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)