-
1
-
-
85027196412
-
-
May 1988
-
K. Sawada, T. Sakurai, K. Nogami, T. lizuka, Y. Uchino, Y. Tanaka, T. Kobayashi, K. Kawagai, E, Ban, Y. Shiotari, Y. Itabashi, and S. Kohyama, "A 72-K CMOS channelless gate array with embedded 1-Mbit dynamic RAM," CICC Digest, pp. 20.3.1-4, May 1988
-
T. Sakurai, K. Nogami, T. Lizuka, Y. Uchino, Y. Tanaka, T. Kobayashi, K. Kawagai, E, Ban, Y. Shiotari, Y. Itabashi, and S. Kohyama, "A 72-K CMOS Channelless Gate Array with Embedded 1-Mbit Dynamic RAM," CICC Digest, Pp. 20.3.1-4
-
-
Sawada, K.1
-
2
-
-
11644259287
-
-
May 1992
-
D. G. Elliott, W. M. Snelgrove, and M. Stumm, "Computational RAM: A memory-SIMD hybrid and its application to DSP," CICC Digest, pp. 36.6.1-4, May 1992
-
W. M. Snelgrove, and M. Stumm, "Computational RAM: a Memory-SIMD Hybrid and Its Application to DSP," CICC Digest, Pp. 36.6.1-4
-
-
Elliott, D.G.1
-
3
-
-
85027123772
-
-
June 1992
-
T. Watanabe, K. Kimura, M. Aoki, T. Sakata, and K. Itoh, "1.5-V digital chip for a 106 -synapse neural network," International Joint Conference on Neural Networks, Baltimore, Digest II, pp. 7-12, June 1992
-
K. Kimura, M. Aoki, T. Sakata, and K. Itoh, "1.5-V Digital Chip for a 106 -Synapse Neural Network," International Joint Conference on Neural Networks, Baltimore, Digest II, Pp. 7-12
-
-
Watanabe, T.1
-
4
-
-
0027590095
-
-
May 1993
-
T. Watanabe, K. Kimura, M. Aoki, T. Sakata, and K. Itoh, "1.5-V digital chip architecture for a I06 -synapse neural network," IEEE Trans. Neural Networks, vol. 4, no. 3, pp. 387-393, May 1993
-
K. Kimura, M. Aoki, T. Sakata, and K. Itoh, "1.5-V Digital Chip Architecture for a I06 -Synapse Neural Network," IEEE Trans. Neural Networks, Vol. 4, No. 3, Pp. 387-393
-
-
Watanabe, T.1
-
5
-
-
0028756450
-
-
" IEICE Trans. Electron., vol. E77-C, no. 12, pp. 1181-1187, Dec. 1994.
-
T. Watanabe, K. Ayukawa, and Y. Nakagome, "3-D CG media chip: An experimental single-chip architecture for three-dimensional computer graphics," IEICE Trans. Electron., vol. E77-C, no. 12, pp. 1181-1187, Dec. 1994.
-
K. Ayukawa, and Y. Nakagome, "3-D CG Media Chip: an Experimental Single-chip Architecture for Three-dimensional Computer Graphics
-
-
Watanabe, T.1
-
6
-
-
0029256368
-
-
Feb. 1995.
-
S. Miyano, K. Numata, K. Sato, T. Yabe, M. Wada, R. Haga, M. Enkaku, M. Shiochi, Y. Kawashima, M. Iwase, M. Ohgata, J. Kumagai, T. Yoshida, M. Sakurai, S. Kaki, N. Yanagiya, H. Shnya, T. Furuyama, P. Hansen, M. Hannah, M. Nagy, A. Nagarajan, and M. Rungsea, "A 1.6-GB/s data-transfer-rate 8-Mb embedded DRAM," ISSCC95, Digest, pp. 300-301, Feb. 1995.
-
K. Numata, K. Sato, T. Yabe, M. Wada, R. Haga, M. Enkaku, M. Shiochi, Y. Kawashima, M. Iwase, M. Ohgata, J. Kumagai, T. Yoshida, M. Sakurai, S. Kaki, N. Yanagiya, H. Shnya, T. Furuyama, P. Hansen, M. Hannah, M. Nagy, A. Nagarajan, and M. Rungsea, "A 1.6-GB/s Data-transfer-rate 8-Mb Embedded DRAM," ISSCC95, Digest, Pp. 300-301
-
-
Miyano, S.1
-
7
-
-
0029252161
-
-
Feb. 1995.
-
K. Inoue, H. Nakamura, H. Kawai, T. Tani, Y. Sakemi, H. Matsuoka, M. Ishikawa, J. Matsumoto, K. Yamamoto, K. Takahashi, M. Yamawaki, E. Yokomoto, C. A. Hart, J. Lin, K. Ishihara, and K. Shimotori, "A 10-Mb 3-D frame buffer memory with Z-compare and alpha-blend units," 1SSCC95, Digest, pp. 302-303, Feb. 1995.
-
H. Nakamura, H. Kawai, T. Tani, Y. Sakemi, H. Matsuoka, M. Ishikawa, J. Matsumoto, K. Yamamoto, K. Takahashi, M. Yamawaki, E. Yokomoto, C. A. Hart, J. Lin, K. Ishihara, and K. Shimotori, "A 10-Mb 3-D Frame Buffer Memory with Z-compare and Alpha-blend Units," 1SSCC95, Digest, Pp. 302-303
-
-
Inoue, K.1
-
8
-
-
0029375722
-
-
Sept. 1995
-
T. Sunaga, H. Miyatake, K. Kitamura, K. Kasuya, T. Saitoh, M. Tanaka, N. Tanigaki, Y. Mori, and N. Yamasaki, "DRAM macros for ASIC chips," IEEE J. Solid-State Circuits, vol.30, no. 9, pp. 1006-1014, Sept. 1995
-
H. Miyatake, K. Kitamura, K. Kasuya, T. Saitoh, M. Tanaka, N. Tanigaki, Y. Mori, and N. Yamasaki, "DRAM Macros for ASIC Chips," IEEE J. Solid-State Circuits, Vol.30, No. 9, Pp. 1006-1014
-
-
Sunaga, T.1
-
9
-
-
0030085960
-
-
Feb. 1996
-
Y. Aimoto, T. Kimura, Y. Yabe, H. Heiuchi, Y. Nakazawa, M. Motomura, T. Koga, Y. Fujita, M. Hamada, T. Tanigawa, H. Nobusawa, and K. Koyama, "A 7.68-G1PS 3.84-GB/s 1-W parallel image-processing RAM integrating a 16-Mb DRAM and 128 processors," ISSCC96, Digest, pp. 372-373, Feb. 1996
-
T. Kimura, Y. Yabe, H. Heiuchi, Y. Nakazawa, M. Motomura, T. Koga, Y. Fujita, M. Hamada, T. Tanigawa, H. Nobusawa, and K. Koyama, "A 7.68-G1PS 3.84-GB/s 1-W Parallel Image-processing RAM Integrating a 16-Mb DRAM and 128 Processors," ISSCC96, Digest, Pp. 372-373
-
-
Aimoto, Y.1
-
10
-
-
0030081181
-
-
Feb. 1996
-
T. Shimizu, J. Korematu, M. Satou, H. Kondo, S. Iwata, K. Sawai, N. Okumura, K. Ishimi, Y. Nakamoto, M. Kumanoya, K. Dosaka, A. Yamazaki, Y. Ajioka, H. Tsubota, Y. Nunomura, T. Urabe, J. Hinata, and K. Saitoh, "A multimedia 32-b RISC microprocessor with 16-Mb DRAM," ISSCC96, Digest, pp. 216-217, Feb. 1996
-
J. Korematu, M. Satou, H. Kondo, S. Iwata, K. Sawai, N. Okumura, K. Ishimi, Y. Nakamoto, M. Kumanoya, K. Dosaka, A. Yamazaki, Y. Ajioka, H. Tsubota, Y. Nunomura, T. Urabe, J. Hinata, and K. Saitoh, "A Multimedia 32-b RISC Microprocessor with 16-Mb DRAM," ISSCC96, Digest, Pp. 216-217
-
-
Shimizu, T.1
-
11
-
-
0029703487
-
-
June 1996
-
[ll] T. Watanabe, R. Fujita, K. Yanagisawa, H. Tanaka, K. Ayukawa, M. Soga, Y. Tanaka, Y. Sugie, and Y. Nakagome, "Modular architecture for a 6.4-Gbyte/s, 8-Mbit media chip," 1996 Symposium on VLSI Circuits, Digest, P. 4.4, June 1996
-
R. Fujita, K. Yanagisawa, H. Tanaka, K. Ayukawa, M. Soga, Y. Tanaka, Y. Sugie, and Y. Nakagome, "Modular Architecture for a 6.4-Gbyte/s, 8-Mbit Media Chip," 1996 Symposium on VLSI Circuits, Digest, P. 4.4
-
-
Watanabe, T.1
-
12
-
-
0031073176
-
-
Feb. 1997
-
D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick, "Intelligent RAM (IRAM): Chips that remember and compute," ISSCC97, Digest, pp. 224-225, Feb. 1997
-
T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick, "Intelligent RAM (IRAM): Chips that Remember and Compute," ISSCC97, Digest, Pp. 224-225
-
-
Patterson, D.1
-
13
-
-
0031070399
-
-
Feb. 1997
-
K. Murakami, S. Shirakawa, and H. Miyajima, "Parallel Processing RAM chip with 256Mb DRAM and quad processors," ISSCC97, Digest, pp. 228-229, Feb. 1997
-
S. Shirakawa, and H. Miyajima, "Parallel Processing RAM Chip with 256Mb DRAM and Quad Processors," ISSCC97, Digest, Pp. 228-229
-
-
Murakami, K.1
-
14
-
-
0031145559
-
-
May 1997
-
T. Watanabe, R. Fujita, K. Yanagisawa, H. Tanaka, K. Ayukawa, M. Soga, Y. Tanaka, Y. Sugie, and Y. Nakagome, "A modular architecture for a 6.4-Gbyte/s, 8Mbit DRAM-integrated media chip," IEEE J. Solid-State Circuits, vol.32, no. 5, pp. 635-641, May 1997
-
R. Fujita, K. Yanagisawa, H. Tanaka, K. Ayukawa, M. Soga, Y. Tanaka, Y. Sugie, and Y. Nakagome, "A Modular Architecture for a 6.4-Gbyte/s, 8Mbit DRAM-integrated Media Chip," IEEE J. Solid-State Circuits, Vol.32, No. 5, Pp. 635-641
-
-
Watanabe, T.1
-
15
-
-
0027631804
-
-
July 1993
-
T. Watanabe, M. Aoki, K. Kimura, T. Sakata, and K. Itoh, "The advantages of a DRAM-based digital architecture for low-power, large-scale neuro-chips," IEICE Trans. Electron., vol. E76-C, no. 7, pp. 1206-1214, July 1993
-
M. Aoki, K. Kimura, T. Sakata, and K. Itoh, "The Advantages of a DRAM-based Digital Architecture for Low-power, Large-scale Neuro-chips," IEICE Trans. Electron., Vol. E76-C, No. 7, Pp. 1206-1214
-
-
Watanabe, T.1
-
16
-
-
0029715043
-
-
June 1996
-
K. Itoh, Y. Nakagome, S. Kimura, and T. Watanabe, "Limitations and challenges of multi-gigabit DRAM circuit," 1996 Symposium on VLSI Circuits, Digest, P. 1. 1, June 1996
-
Y. Nakagome, S. Kimura, and T. Watanabe, "Limitations and Challenges of Multi-gigabit DRAM Circuit," 1996 Symposium on VLSI Circuits, Digest, P. 1. 1
-
-
Itoh, K.1
-
17
-
-
0031343172
-
-
June 1997
-
K. Ayukawa, T. Watanabe, and S. Narita, "An Accesssequence control scheme to enhance random access performance of embedded DRAMs," 1997 Symposium on VLSI Circuits, Digest, P. 8-3, June 1997
-
T. Watanabe, and S. Narita, "An Accesssequence Control Scheme to Enhance Random Access Performance of Embedded DRAMs," 1997 Symposium on VLSI Circuits, Digest, P. 8-3
-
-
Ayukawa, K.1
-
18
-
-
0026853681
-
-
April 1992.
-
A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power CMOS degital design," IEEE J. Solid-State Circuits, vol.27, no. 4, pp. 473-484, April 1992.
-
S. Sheng, and R. W. Brodersen, "Low-power CMOS Degital Design," IEEE J. Solid-State Circuits, Vol.27, No. 4, Pp. 473-484
-
-
Chandrakasan, A.P.1
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