DRAM Macros for ASIC Chips

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 9, 1995, Pages 1006-1014

  Sunaga, Toshio ^a   Miyatake, Hisatada ^a   Kasuya, Keishi ^a   Tanaka, Masahiro ^a   Mori, Yohtaro ^a   Yamasaki, Noritoshi ^a   Kitamura, Koji ^a   Saitoh, Takaki ^a   Tanigaki, Norio ^a  

^a IBM JAPAN LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MACROS; RANDOM ACCESS STORAGE; SEMICONDUCTING SILICON; TRANSISTORS;

CAPACITOR PLATES; DYNAMIC RANDOM ACCESS MEMORY MACROS; TRANSISTOR TRENCH CELLS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0029375722     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.406409     Document Type: Article

References (9)

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