On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 11, 1997, Pages 1735-1742

  Tanoi, Satoru ^a,b,c   Tokunaga, Yasuhiro ^b,d,e   Tanabe, Tetsuya ^b,f   Takahashi, Kazuhiko ^b,g   Okada, Atsuhiko ^b,d,h   Itoh, Masahiro ^b,i,j,k   Nagatomo, Yoshiki ^b,k,l   Ohtsuki, Yoshio ^b,m   Uesugi, Masaru ^b,n,o  

^a IEEE   (Japan)

^b OKI ELECTRIC INDUSTRY CO   (Japan)

^c NIIGATA UNIVERSITY   (Japan)

^d KOBE UNIVERSITY   (Japan)

^e Institute of Electronics   (Japan)

^f Kinki University   (Japan)

^g TOHOKU UNIVERSITY   (Japan)

^h OSAKA UNIVERSITY   (Japan)

ⁱ TOYOHASHI UNIVERSITY OF TECHNOLOGY   (Japan)

^j VLSI Research and Development Center   (Japan)

^k JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

^l YOKOHAMA NATIONAL UNIVERSITY   (Japan)

^m KYOTO UNIVERSITY   (Japan)

ⁿ KYOTO INSTITUTE OF TECHNOLOGY   (Japan)

^o Inst Electronics Commun E

more..

Author keywords

BIST; Compression; DRAM; Gigabit; Search; Test; Word line shunt

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; VECTORS;

BUILT IN SELF TEST TECHNIQUE; ON WAFER TEST MANAGEMENT;

RANDOM ACCESS STORAGE;

EID: 0031270609     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.641694     Document Type: Article

References (14)

1. S. Tanoi et al., "A 32-bank 256-Mb DRAM with cache and TAG," IEEE J. Solid-State Circuits, vol. 29, pp. 1330-1335, Nov. 1994.
2. M. Horiguchi et al., "An experimental 220MHz 1Gb DRAM," in ISSCC Tech. Dig., 1995, pp. 252-253.
3. J. H. Yoo et al., "A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth," IEEE J. Solid-State Circuits, vol. 31, pp. 1635-1644, Nov. 1996.
4. T. Murotani et al., "A 4-level storage 4Gb DRAM," in ISSCC Tech. Dig., 1997, pp. 74-76.
5. S. Mori et al., "A 45-ns 64-Mb DRAM with a merged match-line test architecture," IEEE J. Solid-State Circuits, vol. 26, pp. 1486-1492, Nov. 1991.
6. A. Tanabe et al., "A 30-ns 64-Mb DRAM with built-in self test and self repair function," IEEE J. Solid-State Circuits, vol. 27, pp. 1525-1533, Nov. 1992.
7. N. Sakashita et al., "A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture," IEEE J. Solid-State Circuits, vol. 31, pp. 1645-1655, Nov. 1996.
8. S. Tanoi et al., "On-wafer BIST of 200Gb/s failed-bit search for 1Gb DRAM," in ISSCC Tech. Dig., 1997, pp. 70-71.
9. T. E. Williams et al., "A zero-overhead self-timed 160ns 54b CMOS driver," in ISSCC Tech. Dig., 1991, pp. 98-99.
10. C. H. Stapper et al., "Yield model for productivity optimization of VLSI memory chips with redundancy and partial good product," IBM J. Res. Develop., vol. 24, no. 3, pp. 398-409, May 1980.
11. S. Tanoi et al., "A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture," IEEE J. Solid-State Circuits, vol. 31, pp. 487-493, Apr. 1996.
12. J. G. Maneatis, "Low-jitter and process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
13. M. Nakamura et al., "A 29ns 64Mb DRAM with hierarchical array architecture," in ISSCC Tech. Dig., 1995, pp. 246-247.
14. T. Saeki et al., "A 2.5ns clock access 250MHz 256Mb SDRAM with a synchronous mirror delay," in ISSCC Tech. Dig., 1996, pp. 374-375.