On-wafer BIST of a 200 Gb/s failed-bit search for 1 Gb DRAM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 70-71

  Tanoi, Satoru ^a   Tokunaga, Yasuhiro ^a   Tanabe, Tetsuya ^a   Takahashi, Kazuhiko ^a   Okada, Atsuhiko ^a   Itoh, Masahiro ^a   Nagatomo, Yoshiki ^a   Ohtsuki, Yoshio ^a   Uesugi, Masaru ^a  

^a OKI ELECTRIC INDUSTRY CO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; REDUNDANCY;

BUILT IN SELF TEST (BIST); DYNAMIC RANDOM ACCESS MEMORY (DRAM); FAILED BIT DETECTION METHOD;

RANDOM ACCESS STORAGE;

EID: 0031069027     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)