4.4-ns CMOS 54×54-b multiplier using pass-transistor multiplexer

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1994, Pages 599-602

  Ohkubo, Norio ^a   Suzuki, Makoto ^a   Shinbo, Toshinobu ^a   Yamanaka, Toshiaki ^a   Shimizu, Akihiro ^a   Sasaki, Katsuro ^a   Nakagome, Yoshinobu ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; CMOS INTEGRATED CIRCUITS; CRITICAL PATH ANALYSIS; DIGITAL ARITHMETIC; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; STATE ASSIGNMENT; TREES (MATHEMATICS);

BOOTH ALGORITHM; CARRY LOOK AHEAD ADDER; MANTISSA MULTIPLICATION; PASS TRANSISTOR MULTIPLEXER; WALLACES TREE;

MULTIPLEXING EQUIPMENT;

EID: 0028099002     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)