Lean integration: achieving a quantum leap in performance and cost of logic LSIs

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1994, Pages 603-606

  Yano, Kazuo ^a   Sasaki, Yasuhiko ^a   Rikino, Kunihito ^a   Seki, Koichi ^a  

^a ULSI Research Cent ^*  (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; ELECTRIC INVERTERS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MINIMIZATION OF SWITCHING NETS; MULTIPLEXING EQUIPMENT; REDUCED INSTRUCTION SET COMPUTING;

CIRCUIT INVENTOR; LEAN CELL; LEAN INTEGRATION; LOGIC SYNTHESIS; POWER DISSIPATION;

LSI CIRCUITS;

EID: 0028015166     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)