A 1.5 ns 32 b CMOS ALU in double pass-Transistor logic

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1993, Pages 90-91

  Suzuki, M ^a   Ohkubo, N ^a   Yamanaka, T ^a   Shimizu, A ^b   Sasaki, K ^a  

^a HITACHI LTD   (Japan)

^b Hitachi VLSl Engineering Corp ^*  (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CARRY LOGIC; CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS;

ARITHMETIC AND LOGIC UNITS; CMOS TECHNOLOGY; DOUBLE PASS TRANSISTOR LOGIC; LOW VOLTAGES; MEASURED SPEED; RING OSCILLATOR; SUPPLY VOLTAGES;

COMPUTER CIRCUITS;

EID: 85060884542     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1993.280071     Document Type: Conference Paper

References (2)

1. Yano, K., et al., "A3.8-ns CMOS 16x16-bMultiplier Using Complementary Pass-Transistor Logic", IEEE J. Solid-state Circuits, vol. 25, pp. 388-395, April 1990.
2. Rothermel, A., et al., "Realization of Transmission-Gate Conditional-Sum (TGCS) Adders with Low Latency Time", IEEE J. Solid-State Circuits, vol. 24, pp. 558-561, June 1989.