Spert-II: A Vector microprocessor system

Computer

Volumn 29, Issue 3, 1996, Pages 79-86

  Wawrzynek, John ^a,b,c,d,e   Asanović, Krste ^a,f,g,h   Kingsbury, Brian ^a,i,j   Johnson, David ^b,g   Beck, James ^b,d   Morgan, Nelson ^b,c,h  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTERNATIONAL COMPUTER SCIENCE INSTITUTE   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^e UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^f GEC Hirst Research Center   (United Kingdom)

^g UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^h IEEE

ⁱ MICHIGAN STATE UNIVERSITY   (United States)

^j Tau Beta Pi ^*

more..

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER WORKSTATIONS; INTERFACES (COMPUTER); NEURAL NETWORKS; RANDOM ACCESS STORAGE; REDUCED INSTRUCTION SET COMPUTING; SPEECH RECOGNITION;

SYNTHETIC PERCEPTRON TESTBED II; TORRENT VECTOR MICROPROCESSOR; VECTOR MICROPROCESSOR SYSTEM;

MICROCOMPUTERS;

EID: 0030106918     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.485896     Document Type: Review

References (8)

1. N. Morgan and H. Bourlard, "An Introduction to Connectionist Speech Recognition," Signal Processing Magazine, Vol. 12, No. 3, May 1995, pp. 25-42.
2. J. Wawrzynek, K. Asanović, and N. Morgan, "The Design of a Neuromicroprocessor," IEEE Trans. Neural Networks, Vol. 4, No. 3, 1993, pp. 394-399.
3. G. Kane and J. Heinrich, MIPS RISC Architecture, Prentice Hall, Englewood Cliffs, N.J., 1992.
4. K. Asanovic and N. Morgan, "Experimental Determination of Precision Requirements for Back-Propagation Training of Artificial Neural Networks," Proc. Second Int'l. Conf. Microelectronics for Neural Networks, Kyrill and Method Verlag, Munich, Germany, 1991, pp. 9-16.
5. D. Hammerstrom, "A VLSI Architecture for High-Performance, Low-Cost, On-Chip Learning," Proc. Int'l. Joint Conf. Neural Networks, IEEE Neural Networks Council, Ann Arbor, Mich., 1990, pp. II-537-II-543.
6. U. Ramacher et al., "Design of a First Generation Neurocomputer," in VLSI Design of Neural Networks, U. Ramacher and U. Ruckert, eds., Kluwer Academic, London, 1991, pp. 271-310.
7. N. Morgan et al., "The Ring Array Processor (RAP): A Multiprocessing Peripheral for Connectionist Applications," J. Parallel and Distributed Computing, Vol. 14, No. 3, Mar. 1992, pp. 248-259.
8. "TMS320C80 Multimedia Video Processor," tech. brief, Texas Instruments, Dallas, 1994.