A side-wall transfer-transistor cell (SWATT Cell) for highly reliable multi-level NAND EEPROM's

IEEE Transactions on Electron Devices

Volumn 44, Issue 1, 1997, Pages 145-152

  Aritome, Seiichi ^a   Takeuchi, Yuji ^a   Sato, Shinji ^b   Watanabe, Hiroshi ^b   Shimizu, Kazuhiro ^b   Hemink, Gertjan ^b   Shirota, R ^b  

^a TOSHIBA CORPORATION   (Japan)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; COST EFFECTIVENESS; EQUIVALENT CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; NAND CIRCUITS; PROM; SEMICONDUCTOR STORAGE; VOLTAGE DISTRIBUTION MEASUREMENT;

ELECTRICALLY ERASABLE AND PROGRAMMABLE READ ONLY MEMORY; PASS TRANSISTORS; SHALLOW TRENCH ISOLATION (STI) REGION; SIDE WALL TRANSFER TRANSISTOR (SWATT) CELL; THRESHOLD VOLTAGE;

FIELD EFFECT TRANSISTORS;

EID: 0030735606     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.554804     Document Type: Article

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