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Volumn 12, Issue 6, 1993, Pages 802-809

Robust and Accurate Hierarchical Floorplanning with Integrated Global Wiring

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WIRING; HIERARCHICAL SYSTEMS; OPTIMIZATION; PARAMETER ESTIMATION; ROBUSTNESS (CONTROL SYSTEMS); TREES (MATHEMATICS);

EID: 0027610398     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.229754     Document Type: Article
Times cited : (9)

References (25)
  • 1
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  • 3
    • 0000359078 scopus 로고
    • Simultaneous floorplanning and global routing for hierarchical building block layout
    • W.W.M. Dai and E. S. Kuh, “Simultaneous floorplanning and global routing for hierarchical building block layout,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 828–827, 1987.
    • (1987) IEEE Trans. Computer-Aided Design , vol.CAD-6 , pp. 827-828
    • Dai, W.W.M.1    Kuh, E.S.2
  • 5
    • 84941444794 scopus 로고    scopus 로고
    • Context-sensitive tile compaction of finite two-dimensional cell arrays
    • Paderborn, Germany, in preparation
    • J. Heistermann and T. Lengauer, “Context-sensitive tile compaction of finite two-dimensional cell arrays,” in Dep. Math. Computer Sci. Univ. of Paderborn, Paderborn, Germany, in preparation.
    • Dep. Math. Computer Sci. Univ. of Paderborn
    • Heistermann, J.1    Lengauer, T.2
  • 8
    • 84941477754 scopus 로고
    • Berucksichtigung von vorplazierten Blocken beim Floorplanning basierend auf rekursiven Schaltkreispartitionen
    • D. Kludzeweit, “Bercksichtigung von vorplazierten Blcken beim Floorplanning basierend auf rekursiven Schaltkreispartitionen,” Master’s thesis, Univ. Paderborn, Paderborn, Germany, 1990.
    • (1990) Master's thesis, Univ. Paderborn, Paderborn, Germany
    • Kludzeweit, D.1
  • 9
    • 0022792705 scopus 로고
    • Mason: A global floorplanning approach for VLSI design
    • D. P. La Potin and S. W. Director, “Mason: A global floorplanning approach for VLSI design,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 477–489, 1986.
    • (1986) IEEE Trans. Computer-Aided Design , vol.CAD-5 , pp. 477-489
    • La Potin, D.P.1    Director, S. W.2
  • 10
    • 0001528317 scopus 로고
    • Top down hierarchical global routing for channelless gate arrays based on linear assignment
    • U. Lauther, “Top down hierarchical global routing for channelless gate arrays based on linear assignment,” in Proc. VLSI’87, pp. 141 – 151, 1987.
    • (1987) Proc. VLSI'87 , pp. 141-151
    • Lauther, U.1
  • 16
    • 0025545056 scopus 로고
    • Congestion-driven placement using a new multipartitioning heuristic
    • S. Mayrhofer and U. Lauther, “Congestion-driven placement using a new multipartitioning heuristic,” in Proc. Int. Conf. on Computer-Aided Design, pp. 332–335, 1990.
    • (1990) Proc. Int. Conf. on Computer-Aided Design , pp. 332-335
    • Mayrhofer, S.1    Lauther, U.2
  • 20
    • 0020746257 scopus 로고
    • Optimal orientations of cells in slicing floorplan design
    • L. Stockmeyer, “Optimal orientations of cells in slicing floorplan design,” Inform. Cont., vol. 57, 91–101, 1983.
    • (1983) Inform. Cont. , vol.57 , pp. 91-101
    • Stockmeyer, L.1
  • 21
    • 0025532048 scopus 로고
    • New algorithms for the placement and routing of macro cells
    • W. Swartz and C. Sechen, “New algorithms for the placement and routing of macro cells,” in IEEE Int. Conf. on Computer-Aided Design, pp. 336–339, 1990.
    • (1990) IEEE Int. Conf. on Computer-Aided Design , pp. 336-339
    • Swartz, W.1    Sechen, C.2
  • 23
    • 84941467970 scopus 로고
    • PLEXUS: A system for implementing hierarchical graph algorithms
    • also. Springer Lecture Notes in Computer Science, no. 294, Springer Verlag, New York
    • E. Wanke, “PLEXUS: A system for implementing hierarchical graph algorithms,” in Proc. Fifth Ann. Symp. on Theoretical Aspects of Computer Science, pp. 403-404; also. Springer Lecture Notes in Computer Science, no. 294, Springer Verlag, New York, 1988.
    • (1988) Proc. Fifth Ann. Symp. on Theoretical Aspects of Computer Science , Issue.294 , pp. 403-404
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  • 24
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    • Top-down design of digital systems
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    • G. Zimmermann, “Top-down design of digital systems,” in Advances in CAD for VLSI, Volume 2: Logic Design and Simulation, E. Hrbst, Ed. New York: North-Holland, pp. 185–206, 1986.
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  • 25
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    • A new area and shape function estimation technique for VLSI layouts
    • —, “A new area and shape function estimation technique for VLSI layouts,” IEEE/ACM Proc. 25th Design Automation Conf., pp. 60–65, 1988.
    • (1988) IEEE/ACM Proc. 25th Design Automation Conf. , pp. 60-65


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.