메뉴 건너뛰기




Volumn 12, Issue 5, 1993, Pages 599-620

Algorithms for Technology Mapping Based on Binary Decision Diagrams and on Boolean Operations

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; DECISION THEORY; LOGIC DESIGN;

EID: 0027591119     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.277607     Document Type: Article
Times cited : (64)

References (43)
  • 8
    • 0023210698 scopus 로고
    • Dagon: Technology binding and local optimization by dag matching
    • K. Keutzer, “Dagon: Technology binding and local optimization by dag matching,” in 24th Design Automation Conf, IEEE/ACM, pp. 341–347, 1987.
    • (1987) 24th Design Automation Conf, IEEE/ACM , pp. 341-347
    • Keutzer, K.1
  • 9
    • 0024142721 scopus 로고
    • Mapping properties of multi-level logic synthesis operations
    • Oct.
    • M. C. Lega, “Mapping properties of multi-level logic synthesis operations,” in Int. Conf. Computer Design, IEEE, pp. 257–261, Oct. 1988.
    • (1988) Int. Conf. Computer Design, IEEE , pp. 257-261
    • Lega, M.C.1
  • 10
    • 0024136038 scopus 로고
    • Mcmap: A fast technology mapping procedure for multi-level logic synthesis
    • Oct.
    • R. Lisanke, F. Brglez, and G. Kedem, “Mcmap: A fast technology mapping procedure for multi-level logic synthesis,” in Int. Conf. Computer Design, IEEE, pp. 252–256, Oct. 1988.
    • (1988) Int. Conf. Computer Design, IEEE , pp. 252-256
    • Lisanke, R.1    Brglez, F.2    Kedem, G.3
  • 11
    • 33746945819 scopus 로고
    • Techmap: Technology mapping with delay and area optimization
    • G. Saucier and P. M. McLellan, Eds. New York: North-Holland
    • C. R. Morrison, R. M. Jacoby, and G. D. Hachtel, “Techmap: Technology mapping with delay and area optimization,” in Logic and Architecture Synthesis for Silicon Compilers, G. Saucier and P. M. McLellan, Eds. New York: North-Holland, 1989, pp. 53–64.
    • (1989) Logic and Architecture Synthesis for Silicon Compilers , pp. 53-64
    • Morrison, C.R.1    Jacoby, R.M.2    Hachtel, G.D.3
  • 12
    • 0003623384 scopus 로고
    • Logic synthesis for VLSI design
    • U. C. Berkeley (Memorandum UCB/ERL M89/49), Apr.
    • R. Rudell, “Logic synthesis for VLSI design,” Ph.D. dissertation, U. C. Berkeley (Memorandum UCB/ERL M89/49), Apr. 1989.
    • (1989) Ph.D. dissertation
    • Rudell, R.1
  • 13
    • 0017983865 scopus 로고
    • Binary decision diagrams
    • June
    • S. B. Akers, “Binary decision diagrams,” IEEE Trans. Computers, vol. 27, pp. 509–516, June 1978.
    • (1978) IEEE Trans. Computers , vol.27 , pp. 509-516
    • Akers, S.B.1
  • 14
    • 0022769976 scopus 로고
    • Graph-based algorithms for Boolean function manipulation
    • Aug.
    • R. E. Bryant, “Graph-based algorithms for Boolean function manipulation,” IEEE Trans. Computers, vol. 35, pp. 677–691, Aug. 1986.
    • (1986) IEEE Trans. Computers , vol.35 , pp. 677-691
    • Bryant, R.E.1
  • 18
    • 84926299170 scopus 로고
    • Detection of group invariance or total symmetry of a Boolean function
    • Nov.
    • E. J. McCluskey, “Detection of group invariance or total symmetry of a Boolean function,” Bell Syst. Tech J., vol. 35, pp. 1445–1453, Nov. 1956.
    • (1956) Bell Syst. Tech J. , vol.35 , pp. 1445-1453
    • McCluskey, E.J.1
  • 24
    • 0024904942 scopus 로고
    • Consistency and observability invariance in multi-level logic synthesis
    • Nov.
    • P. McGeer and R. K. Brayton, “Consistency and observability invariance in multi-level logic synthesis,” in Int. Conf. Computer-Aided Design, IEEE, pp. 426–429, Nov. 1989.
    • (1989) Int. Conf. Computer-Aided Design, IEEE , pp. 426-429
    • McGeer, P.1    Brayton, R.K.2
  • 27
    • 84941435711 scopus 로고
    • The use of image computation techniques in extracting local don't cares and network optimization
    • Nov.
    • H. Savoj, R.K. Brayton, and H. Touati, “The use of image computation techniques in extracting local don't cares and network optimization,” in Int. Conf Computer-Aided Design, IEEE, Nov. 1991.
    • (1991) Int. Conf Computer-Aided Design, IEEE
    • Savoj, H.1    Brayton, R.K.2    Touati, H.3
  • 28
    • 84941472709 scopus 로고    scopus 로고
    • Private communication, Apr.
    • H. Savoj, Private communication, Apr. 1991.
    • Savoj, H.1
  • 29
    • 84894500097 scopus 로고    scopus 로고
    • Technology mapping for VLSI circuits exploiting Boolean properties and operations
    • Ph.D. dissertation, Stanford University, Dec.
    • F. Mailhot, “Technology mapping for VLSI circuits exploiting Boolean properties and operations,” Ph.D. dissertation, Stanford University, Dec. 1991.
    • Mailhot, F.1
  • 30
  • 31
    • 0025561399 scopus 로고
    • The use of observability and external don't cares for the simplification of multi-level networks
    • June
    • H. Savoj and R. K. Brayton, “The use of observability and external don't cares for the simplification of multi-level networks,” in Design Automation Conf., ACM/IEEE, pp. 297–301, June 1990.
    • (1990) Design Automation Conf. ACM/IEEE , pp. 297-301
    • Savoj, H.1    Brayton, R.K.2
  • 32
    • 84941461822 scopus 로고
    • Derivation of don't care conditionsby perturbation analysis of combinational multiple-level logic circuits
    • May
    • M. Damiani and G. D. Micheli, “Derivation of don't care conditions by perturbation analysis of combinational multiple-level logic circuits,” in Int. Workshop Logic Synth., MCNC, p. 6.1a, May 1991.
    • (1991) Int. Workshop Logic Synth., MCNC , pp. 6.1a
    • Damiani, M.1    Micheli, G.D.2
  • 34
    • 84941444032 scopus 로고
    • Increased CMOS IC stuck-at fault coverage with reduced IDDQtest sets
    • R. R. Fritzemeir, J. Soden, R. K. Treece, and C. Hawkins, “Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets,” in Int. Test Conf., IEEE, pp. 427–435, 1960.
    • (1960) Int. Test Conf., IEEE , pp. 427-435
    • Fritzemeir, R.R.1    Soden, J.2    Treece, R.K.3    Hawkins, C.4
  • 35
  • 37
    • 0019896149 scopus 로고
    • Timing analysis of computer hardware
    • Jan.
    • R. Hitchcock, G. Smith, and D. Cheng, “Timing analysis of computer hardware,” IBM J. Res. Develop., vol. 26, pp. 100–105, Jan. 1982.
    • (1982) IBM J. Res. Develop. , vol.26 , pp. 100-105
    • Hitchcock, R.1    Smith, G.2    Cheng, D.3
  • 38
    • 0001893927 scopus 로고
    • Performance-oriented synthesis in the Yorktown silicon compiler
    • Sept.
    • G. De Micheli, “Performance-oriented synthesis in the Yorktown silicon compiler,” IEEE Trans. Computer-Aided Design, pp. 751–765, Sept. 1987.
    • (1987) IEEE Trans. Computer-Aided Design , pp. 751-765
    • De Micheli, G.1
  • 42
    • 0024882159 scopus 로고
    • Logic decomposition algorithms for the timing optimization of multi-level logic
    • June
    • P. G. Paulin and F. J. Poirot, “Logic decomposition algorithms for the timing optimization of multi-level logic,” in 26th Design Automation Conf., IEEE/ACM, pp. 329–333, June 1989.
    • (1989) 26th Design Automation Conf., IEEE/ACM , pp. 329-333
    • Paulin, P.G.1    Poirot, F.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.