Performance driven bus buffer insertion

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 4, 1996, Pages 429-437

  Tsai, Chia Chun ^a   Kao, De Yu ^a   Cheng, Chung Kuan ^a  

^a NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; ELECTRIC DELAY LINES; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; PERFORMANCE; TOPOLOGY;

BUFFER INSERTION; MULTISOURCE MULTISINK BUS; SIGNAL DELAY TIME;

COMPUTER AIDED DESIGN;

EID: 0030121032     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.494706     Document Type: Article

References (19)

1. J. P. Fishburn and A. E. Dunlop, "T1LOS: A posynomial programming approach to transistor sizing," in Proc. IEEE Int. Conf. Computer-Aided Design, 1985, pp. 326-328.
2. P. K, Chan, "Algorithm for library-specific sizing of combinational logic," in Proc. 27lh ACM/IEEE Design Automation Conf., 1990, pp. 353-356.
3. M. R. C. M. Berkelaar and J. A. G. Jess, "Gate sizing in MOS digital circuits with linear programming," in Proc. Euro. Design Automation Conf., 1990, pp. 217-221.
4. A. C. H. Wu, N. Vander Zanden, and D. Gajski, "A new algorithm for transistor sizing in CMOS circuit," in Proc. Euro. Design Automation Conf., 1990, pp. 589-593.
5. S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Rang, "An exact solution to the transistor sizing problem for CMOS circuits using convex optimization," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1621-1634, Nov. 1993.
6. S. Mehrotra, P. Franzin, and W. Liu, "Stochastic optimization approach to transistor sizing for CMOS VLSI circuits," in Proc. 31st ACM/IEEE Design Automation Conf., 1994, pp. 36-40.
7. L. V. Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. Int. Symp. Circuits Syst., 1990, pp. 865-868.
8. J. D. Cho and M. Sarrafzadeh. "A buffer distribution algorithm for high-speed clock routing," in Proc. 30th ACM/IEEE Design Automation Conf., 1993, pp. 537-543.
9. S. Pullela, N. Menezes, J. Omar, and L. Pillage, "Skew and delay optimization for reliable buffered clock trees," in Proc. IEEE Int. Conf. Computer-Aided Design, 1993, pp. 556-562.
10. J. Chung and C. K. Cheng, "Skew sensitivity minimization of buffered clock tree," in Proc. of IEEE Int. Conf. Computer Aided Design. 1994, pp. 280-283.
11. S. Lin and B. W. Kernighan, "Heuristic solution of a concentrator location problem," Bell Lab. Tech. Memo., 1976.
12. S. Lin, "Effective use of heuristic algorithms in network design," in Proc. Symp. Appl. Math., vol. 26, 1982, pp. 63-84.
13. T. B. Huang, Y. C. Jeng, and K. Lofstrom, "Bi-directional bus repeater," U.S. Patent US005202593A, Apr. 1993.
14. W. C. Elmore, "The transient response of damped linear networks with particular regard to wide-band amplifiers," J. Appl. Phys., vol. 19, no. 1, pp. 55-63, Jan. 1948.
15. C. S. Beightler and D. T. Phillips, Applied Geometric Programming. New York: Wiley, 1976.
16. S. Lin and B. W. Kernighan, "An effective heuristic algorithm for the traveling salesman problem," Operations Res., vol. 21, no. 2, pp. 498-516, 1973.
17. S. Lin, "Heuristic programming as an aid to network design," Networks, vol. 5, no. 1, pp. 335, Jan. 1975.
18. Sergio Pissanetsky, Sparse Matrix Technology. London, England: Academic, 1984.
19. NCR ASK Data Book, NCR Corp., Dayton, OH, Jan. 1987.