Skew sensitivity minimization of buffered clock tree

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 280-283

  Chung, Jae ^a   Cheng, Chung Kuan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DELAY CIRCUITS; DYNAMIC PROGRAMMING; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WIRE; ELECTRIC WIRING; RESPONSE TIME (COMPUTER SYSTEMS); SENSITIVITY ANALYSIS; TREES (MATHEMATICS);

BUFFER SIZES; BUFFERED CLOCK TREE; CLOCK SIGNALS; RUN TIME; SKEW SENSITIVITY MINIMIZATION;

BUFFER CIRCUITS;

EID: 0028727541     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (11)