BDD-based spectral approach for Reed-Muller circuit realisation

IEE Proceedings: Computers and Digital Techniques

Volumn 143, Issue 2, 1996, Pages 145-150

  Thornton, M A ^a   Nair, V S S ^a  

^a UNIVERSITY OF ARKANSAS   (United States)

Author keywords

Binary decision diagram; Reed muller circuits; Spectral coefficients

Indexed keywords

ALGORITHMS; BINARY SEQUENCES; BOOLEAN ALGEBRA; CALCULATIONS; COMPUTATIONAL METHODS; LOGIC GATES; MATHEMATICAL TECHNIQUES; SPECTRUM ANALYSIS;

BINARY DECISION DIAGRAM; OUTPUT PROBABILITY EXPRESSION; REED-MULLER CIRCUITS; SPECTRAL COEFFICIENTS;

LOGIC CIRCUITS;

EID: 0030105547     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19960067     Document Type: Article

References (15)

1. SASAO, T., and BESSLICH, P.: 'On the complexity of mod-2 sum PLAs', IEEE Trans., 1990, C-39, (2), pp. 262-266
2. ROLLWAGE, U.R.: 'The complexity of mod-2 sum PLA's for symmetric functions'. Proceedings IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, September 1993, pp. 6-12
3. REDDY, S.M.: 'Easily testable realizations for logic functions', IEEE Trans., 1972, C-21, (11), pp. 1183-1188
4. SARABI, A., and PERKOWSKI, M.: 'Fast exact quasi-minimal minimization of highly testable fixed-polarity ANDXOR canonical networks'. Proceedings of the IEEE Design Automation Conference, 1992, pp. 30-35
5. THORNTON, M.A., and NAIR, V.S.S.: 'Efficient spectral coefficient calculation using circuit output probabilities', Digital Sig. Proc.: Rev. J., 1994, pp. 245-254
6. BARTEE, T.C., LEBOW, I.L., and REED, I.S.: Theory and design of digital machines' (McGraw-Hill, New York, 1962)
7. LARNEY, V.H.: 'Abstract algebra a first course' (Prindle, Weber, and Schmigt, Boston, MA, 1975)
8. GREEN, D.: 'Modern logic desicn' (Addison-Wesley, Reading, MA, 1986)
9. DAVIÖ", M., DESCHAMPS, J.-P., and THAYSE, A.: 'Discrete and switching functions' (McGraw-Hill, New York, 1978)
10. PARKER, K.P., and MCCLUSKEY, E.J.: 'Probabilistic treatment of general combinational networks', IEEE Trans., 1975, C24, pp. 668-670
11. BRYANT, R.E.: 'Graph-based algorithms for Boolean function manipulation', IEEE Trans., 1986, C-35, (8), pp. 677-691
12. AKERS, S.B.: 'Binary decision diagrams', IEEE Trans., 1978, C27, (6), pp. 509-516
13. DEVADAS, S.: 'Comparing two-level and ordered binary decision diagram representations of logic functions', IEEE Trans. CAD Integrated Circuits and Systems, 1993, 12, (5), pp. 722-723
14. BRYANT, R.: 'On the complexity of VLSI implementations and graph representations of Boolean functions with applications to integer multiplication', IEEE Trans. Comput., 1991, 40, (2), pp. 205-213
15. MINATO, S., ISHIURA, N., and YAJIMA, S.: 'Shared binary design diagram with attributed edges for efficient Boolean function manipulation'. Proceedings of the ACM/IEEE Design Automation Conference, 1990, pp. 52-57