Easily testable realizations for logic functions

IEEE Transactions on Computers

Volumn C-21, Issue 11, 1972, Pages 1183-1188

  Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

Easily testable networks; fault detection; Reed Muller canonic expressions; single faults; stuck at faults

Indexed keywords

COMPUTERS - RELIABILITY; LOGIC CIRCUITS;

FAULT TOLERANT MACHINES;

COMPUTER METATHEORY;

EID: 0015434912     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1972.223475     Document Type: Article

References (6)

1. D. E. Muller, “Application of Boolean algebra to switching circuit design and to error detection,” IRE Trans. Electron. Comput., vol. EC-3, pp. 6–12, Sept. 1954.
2. A. Mukhopadhyay and G. Schmitz, “Minimization of exclusive or and logical EQUIVALENCE switching circuits,” IEEE Trans. Comput., vol. C-19, pp. 132–140, Feb. 1970.
3. W. H. Kautz, “Testing faults in combinational cellular logic arrays,” in Proc. 8th Annu. Symp. Switching and Automata Theory, Oct. 1971, pp. 161–174.
4. A. D. Friedman, “Fault detection in redundant circuits,” IEEE Trans. Electron. Comput. (Short Notes), vol. EC-16, pp. 99–100, Feb. 1967.
5. S. M. Reddy, “Easily testable realizations for logic functions,” Dep. Math., Univ. Iowa, Iowa City, Themis Rep. 54, May 1972.
6. “, “Fault locatable two dimensional cellular logic arrays,” in Proc. 6th Annu. Princeton Conf. Inform. Sci. Sys., Mar. 1972.