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Volumn 39, Issue 2, 1990, Pages 262-266

On the Complexity of Mod-2 Sum PLA’s

Author keywords

Complexity; easily testable circuits; Exclusive OR sumof products; functions; logic minimization; programmable logic array; symmetric

Indexed keywords

COMPUTER PROGRAMMING--ALGORITHMS; OPTIMIZATION;

EID: 0025387007     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.45212     Document Type: Article
Times cited : (131)

References (26)
  • 1
    • 0019609761 scopus 로고
    • Multiple-valued decomposition of generalized Boolean functions and the complexity of programmable logic arrays
    • Sept.
    • T. Sasao, “Multiple-valued decomposition of generalized Boolean functions and the complexity of programmable logic arrays,” IEEE Trans. Comput., vol. C-30, pp. 635-643, Sept. 1981.
    • (1981) IEEE Trans. Comput. , vol.C-30 , pp. 635-643
    • Sasao, T.1
  • 2
    • 0021510779 scopus 로고
    • Input variable assignment and output phase optimization of PLA’s
    • Oct.
    • —, “Input variable assignment and output phase optimization of PLA’s,” IEEE Trans. Comput., vol. C-33, pp. 879-894, Oct. 1984.
    • (1984) IEEE Trans. Comput. , vol.C-33 , pp. 879-894
  • 3
    • 0001652787 scopus 로고
    • On minimal modulo-2 sums of products for switching functions
    • Oct.
    • S. Even, I. Kohavi, and A. Paz, “On minimal modulo-2 sums of products for switching functions,” IEEE Trans. Electron. Comput., vol. EC-16, pp. 671-674, Oct. 1967.
    • (1967) IEEE Trans. Electron. Comput. , vol.EC-16 , pp. 671-674
    • Even, S.1    Kohavi, I.2    Paz, A.3
  • 4
    • 0014737760 scopus 로고
    • Minimization of Exclusive  OR and logical equivalence of switching circuits
    • A. Mukhopadhyay and G. Schmitz, “Minimization of Exclusive  OR and logical equivalence of switching circuits,” IEEE Trans. Comput., vol. C-19, pp. 132-140, 1970.
    • (1970) IEEE Trans. Comput. , vol.C-19 , pp. 132-140
    • Mukhopadhyay, A.1    Schmitz, G.2
  • 5
    • 0020165896 scopus 로고
    • A method for modulo-2 minimization
    • J. P. Robinson and C.-L. Yeh, “A method for modulo-2 minimization,” IEEE Trans. Comput., vol. C-31, pp. 800-801, 1982.
    • (1982) IEEE Trans. Comput. , vol.C-31 , pp. 800-801
    • Robinson, J.P.1    Yeh, C.-L.2
  • 6
    • 0020992972 scopus 로고
    • On the realization of multiple-valued logic functions using CCD PLA’s
    • May
    • P. Tirumalai and J. T. Butler, “On the realization of multiple-valued logic functions using CCD PLA’s,” in Proc. 14 Int. Symp. Multiple - Valued Logic, May 1984, pp. 33-42.
    • (1984) Proc. 14 Int. Symp. Multiple - Valued Logic , pp. 33-42
    • Tirumalai, P.1    Butler, J.T.2
  • 8
    • 84941486635 scopus 로고
    • On the complexity of PLA’s with EXOR arrays
    • Nov.
    • T. Sasao and P. W. Besslich, “On the complexity of PLA’s with EXOR arrays,” IECEJ Tech. Rep., FTS 86-17, Nov. 1986.
    • (1986) IECEJ Tech. Rep.
    • Sasao, T.1    Besslich, P.W.2
  • 9
    • 9144245836 scopus 로고
    • A class of multiple-error-correcting codes and the decoding scheme
    • I. S. Reed, “A class of multiple-error-correcting codes and the decoding scheme,” IRE Trans. Inform. Theory, vol. PGIT-4, pp. 38-49, 1954.
    • (1954) IRE Trans. Inform. Theory , vol.PGIT-4 , pp. 38-49
    • Reed, I.S.1
  • 10
    • 0002669842 scopus 로고
    • Application of Boolean algebra to switching circuit design and to error detection
    • D. E. Muller, “Application of Boolean algebra to switching circuit design and to error detection,” IRE Trans. Electron. Comput., vol. EC-3, pp. 6-12, 1954.
    • (1954) IRE Trans. Electron. Comput. , vol.EC-3 , pp. 6-12
    • Muller, D.E.1
  • 11
    • 0015586257 scopus 로고
    • Minimization of ring-sum expansions of Boolean functions
    • G. Bioul, M. Davio, and J. P. Deschamps, “Minimization of ring-sum expansions of Boolean functions,” Philips Res. Rep., vol. 28, pp. 17-36, 1973.
    • (1973) Philips Res. Rep. , vol.28 , pp. 17-36
    • Bioul, G.1    Davio, M.2    Deschamps, J.P.3
  • 12
    • 0016926338 scopus 로고
    • Multiple-valued switching circuit design by means of generalized Reed-Muller expansions
    • D. H. Green and I. S. Taylor, “Multiple-valued switching circuit design by means of generalized Reed-Muller expansions,” Digital Processes, vol. 2, pp. 63-81, 1976.
    • (1976) Digital Processes , vol.2 , pp. 63-81
    • Green, D.H.1    Taylor, I.S.2
  • 13
    • 84941476933 scopus 로고    scopus 로고
    • Synthesis of Exclusive- O R logic functions
    • P. W. Besslich and H. Bassmann, “Synthesis of Exclusive- O R logic functions,” Berichte Elekrotechnik, ISSN 0724-1933, No. 3.87, Universitat Bremen, FB-1, P.O. Box 330 440, D-2800 Bremen 33, West Germany.
    • Berichte Elekrotechnik , Issue.3
    • Besslich, P.W.1    Bassmann, H.2
  • 14
    • 0347827653 scopus 로고
    • Spectral processing of switching functions using signal-flow transformations
    • P. W. Besslich, “Spectral processing of switching functions using signal-flow transformations,” Spectral Techniques and Fault Detection, in M. Karpovsky, Ed. Orlando, FL: Academic, 1985, pp. 91-141.
    • (1985) Spectral Techniques and Fault Detection , pp. 91-141
    • Besslich, P.W.1
  • 15
    • 0016102508 scopus 로고
    • MINI: A heuristic approach for logic minimization
    • Sept.
    • S. J. Hong, R. G. Cain, and D. L. Ostapko, “MINI: A heuristic approach for logic minimization,” IBM J. Res. Develop., vol. 18, pp. 443-458, Sept. 1974.
    • (1974) IBM J. Res. Develop. , vol.18 , pp. 443-458
    • Hong, S.J.1    Cain, R.G.2    Ostapko, D.L.3
  • 16
    • 0023289113 scopus 로고
    • A computer algorithm for minimizing Reed-Muller canonical forms
    • Feb.
    • H. Fleisher, M. Tavel, and J. Yeager, “A computer algorithm for minimizing Reed-Muller canonical forms,” IEEE Trans. Comput., vol. C-36, no. 2, pp. 247-250, Feb. 1987.
    • (1987) IEEE Trans. Comput. , vol.C-36 , Issue.2 , pp. 247-250
    • Fleisher, H.1    Tavel, M.2    Yeager, J.3
  • 17
    • 0024136029 scopus 로고
    • A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms
    • June
    • M. Helliwell and M. Perkowski, “A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms,” in Proc. 25th Design Automat. Conf., June 1988, pp. 427-432.
    • (1988) Proc. 25th Design Automat. Conf. , pp. 427-432
    • Helliwell, M.1    Perkowski, M.2
  • 18
    • 84941454601 scopus 로고
    • On a design algorithm for and-EXOR PLA’s with input decoders
    • Jan.
    • T. Sasao and M. Higashida, “On a design algorithm for and-EXOR PLA’s with input decoders,” The 20th FTC Workshop, Jan. 1989 (in Japanese).
    • (1989) The 20th FTC Workshop
    • Sasao, T.1    Higashida, M.2
  • 19
    • 84939359455 scopus 로고
    • Introduction to Switching and Automata Theory
    • M. A. Harrison, Introduction to Switching and Automata Theory. New York: McGraw-Hill, 1965.
    • (1965) New York: McGraw-Hill
    • Harrison, M.A.1
  • 20
    • 84939768261 scopus 로고
    • Logic Design and Switching Theory
    • S. Muroga, Logic Design and Switching Theory. New York: Wiley, 1979.
    • (1979) New York: Wiley
    • Muroga, S.1
  • 21
    • 84941457656 scopus 로고    scopus 로고
    • Table for minimum exclusive- O R sum-of-products for 4-variable functions
    • N. Koda and T. Sasao, “Table for minimum exclusive- O R sum-of-products for 4-variable functions,” in preparation.
    • preparation.
    • Koda, N.1    Sasao, T.2
  • 22
    • 11144342689 scopus 로고
    • A catalog of three-variable OR-invert and AND-invert logical circuits
    • June
    • L. Hellerman, “A catalog of three-variable OR-invert and AND-invert logical circuits,” IEEE Trans. Electron. Comput., vol. EC-12, pp. 198-223, June 1963.
    • (1963) IEEE Trans. Electron. Comput. , vol.EC-12 , pp. 198-223
    • Hellerman, L.1
  • 23
    • 0015434912 scopus 로고
    • Easily testable realization for logic functions
    • S. M. Reddy, “Easily testable realization for logic functions,” IEEE Trans. Comput., vol. C-21, pp. 1083-1088, 1972.
    • (1972) IEEE Trans. Comput. , vol.C-21 , pp. 1083-1088
    • Reddy, S.M.1
  • 24
    • 0019634514 scopus 로고
    • A design procedure of programmable logic arrays with universal tests
    • Nov.
    • H. Fujiwara and K. Kinoshita, “A design procedure of programmable logic arrays with universal tests,” IEEE Trans. Comput., vol. C-30, pp. 823-828, Nov. 1981.
    • (1981) IEEE Trans. Comput. , vol.C-30 , pp. 823-828
    • Fujiwara, H.1    Kinoshita, K.2
  • 26
    • 84941438760 scopus 로고
    • A design of and- EXOR PLA’s with universal tests
    • Feb.
    • T. Sasao and H. Fujiwara, “A design of and- EXOR PLA’s with universal tests,” IECEJ Tech. Rep., FTS 86-26, Feb. 1987 (in Japanese).
    • (1987) IECEJ Tech. Rep.
    • Sasao, T.1    Fujiwara, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.