Comparing Two-Level and Ordered Binary Decision Diagram Representations of Logic Functions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 12, Issue 5, 1993, Pages 722-723

  Devadas, Srinivas ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECISION THEORY; LOGIC DESIGN; VLSI CIRCUITS;

BINARY DECISION DIAGRAMS; LOGIC FUNCTIONS;

LOGIC CIRCUITS;

EID: 0027595269     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.277617     Document Type: Article

References (4)

1. R. K. Brayton, G. D. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Norwell, MA: Kluwer Academic, 1984.
2. R. Bryant, “Graph-based algorithms for Boolean function manipulation,” in IEEE Trans. Computers, vol. C-35, pp. 677–691, Aug. 1986.
3. R. Bryant, “On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication,” in IEEE Trans. Computers, vol. 40, pp. 205–213, Feb. 1991.
4. R. Lipton and R. Sedgewick, “Lower bounds for VLSI,” in Proc. ACM Symp. Theory of Computation, pp, 300–307, June 1981.