-
1
-
-
0014773447
-
Local oxidation of silicon and its application in semiconductor device technology
-
J. Appels, E. Kooi, M. M. Paffen, J. J. H. Schatorje, and W. H. O. O. Verkuylen, "Local oxidation of silicon and its application in semiconductor device technology," Philips Res. Rept, vol. 25, pp. 118-132, 1970.
-
(1970)
Philips Res. Rept
, vol.25
, pp. 118-132
-
-
Appels, J.1
Kooi, E.2
Paffen, M.M.3
Schatorje, J.J.H.4
Verkuylen, W.H.5
-
2
-
-
0017020353
-
Topology of silicon structures with recessed SiC>2
-
E. Bassous, H. H. Yu, and V. Maniscalco, "Topology of silicon structures with recessed SiC>2," J. Electrochem. Soc., vol. 123, no. 11, pp. 1729-1737, 1976.
-
(1976)
J. Electrochem. Soc.
, vol.123
, Issue.11
, pp. 1729-1737
-
-
Bassous, E.1
Yu, H.H.2
Maniscalco, V.3
-
3
-
-
84975449235
-
Formation of silicon nitride at a Si-SiU2 interface during local oxidation of silicon and during heattreatment of oxidized silicon in NHs gas
-
E. Kooi, J. G. Van Lerop, and J. A. Appels, "Formation of silicon nitride at a Si-SiU2 interface during local oxidation of silicon and during heattreatment of oxidized silicon in NHs gas," J. Electrochem, Soc., vol. 123, no. 7, pp. 1117-1120, 1976.
-
(1976)
J. Electrochem, Soc.
, vol.123
, Issue.7
, pp. 1117-1120
-
-
Kooi, E.1
Van Lerop, J.G.2
Appels, J.A.3
-
4
-
-
0019623919
-
Selective oxidation technologies for high density MOS
-
J. Hui, T. Y. Chiu, S. Wong, and W. G. Oldham, "Selective oxidation technologies for high density MOS," IEEE Electron Device Lett., vol. EDL-2, no. 10, pp. 244-247, 1981.
-
(1981)
IEEE Electron Device Lett.
, vol.EDL-2
, Issue.10
, pp. 244-247
-
-
Hui, J.1
Chiu, T.Y.2
Wong, S.3
Oldham, W.G.4
-
5
-
-
0020114646
-
A bird's beak free local oxidation technology feasible for VLSI circuits fabrication
-
K. Y. Chiu, J. L. Moll, and J. Manoliu, "A bird's beak free local oxidation technology feasible for VLSI circuits fabrication," IEEE Trans. Electron Devices, vol. ED-29, no. 4, pp. 536-540, 1982.
-
(1982)
IEEE Trans. Electron Devices
, vol.ED-29
, Issue.4
, pp. 536-540
-
-
Chiu, K.Y.1
Moll, J.L.2
Manoliu, J.3
-
6
-
-
18344399350
-
Isolation process using polysilicon buffer layer for scaled MOS/VLSI
-
Y. P. Han and B. Ma, "Isolation process using polysilicon buffer layer for scaled MOS/VLSI," Electrochem. Soc. Ext. Abstracts, vol. 84-1, p. 98, 1984.
-
(1984)
Electrochem. Soc. Ext. Abstracts
, vol.84
, Issue.1
, pp. 98
-
-
Han, Y.P.1
Ma, B.2
-
7
-
-
0022201692
-
A new isolation technology for VLSI
-
K. Nojiri, K. Tsunokuni, K. Hirobe, A. Koike, K. Ito, and S. Kisino, "A new isolation technology for VLSI," in Extended Abstracts 17th Conf. Solid State Device Materials, 1985, pp. 337-340.
-
Extended Abstracts 17th Conf. Solid State Device Materials
, vol.1985
, pp. 337-340
-
-
Nojiri, K.1
Tsunokuni, K.2
Hirobe, K.3
Koike, A.4
Ito, K.5
Kisino, S.6
-
8
-
-
0022670230
-
A new fully-recessed-oxide (FUROX) field isolation technology for scaled VLSI circuit fabrication
-
H.-H. Tsai, S.-M. Chen, and C.-Y. Wu, "A new fully-recessed-oxide (FUROX) field isolation technology for scaled VLSI circuit fabrication," IEEE Electron Device Leu., vol. EDL-7. pp. 124-126, 1986.
-
(1986)
IEEE Electron Device Leu.
, vol.EDL-7
, pp. 124-126
-
-
Tsai, H.-H.1
Chen, S.-M.2
Wu, C.-Y.3
-
9
-
-
0026123576
-
Polysilicon encapsulated local oxidation
-
S. S. Roth, W. Ray, C. Mazure, and H. C. Kirsch, "Polysilicon encapsulated local oxidation," IEEE Electron Device Lett., vol. 12, no. 3, pp. 92-94, 1991.
-
(1991)
IEEE Electron Device Lett.
, vol.12
, Issue.3
, pp. 92-94
-
-
Roth, S.S.1
Ray, W.2
Mazure, C.3
Kirsch, H.C.4
-
10
-
-
84952890440
-
Nitride-clad LOCOS isolation for 0.25 pm CMOS
-
J. R. Pfiester, P. U. Kenkare, R. Subrahmanyan, J.-H. Lin, and P. Crabtree, "Nitride-clad LOCOS isolation for 0.25 pm CMOS." Symp. on VLSI Tech., 1993, pp. 139-140.
-
Symp. on VLSI Tech.
, vol.1993
, pp. 139-140
-
-
Pfiester, J.R.1
Kenkare, P.U.2
Subrahmanyan, R.3
Lin, J.-H.4
Crabtree, P.5
-
11
-
-
0024931659
-
Characterization of poly-buffered LOCOS in manufacturing environment
-
R. L. Guldi, B. McKec, G. M. Damminga, C. Y. Young, and M. A. Beals, "Characterization of poly-buffered LOCOS in manufacturing environment," J. Electrochem. Soc., vol. 136, no. 12, pp. 3815-3820, 1989.
-
(1989)
J. Electrochem. Soc.
, vol.136
, Issue.12
, pp. 3815-3820
-
-
Guldi, R.L.1
McKec, B.2
Damminga, G.M.3
Young, C.Y.4
Beals, M.A.5
-
12
-
-
0028749054
-
A highly practical modified LOCOS isolation technology for the 256 Mbit DRAM
-
|12] D. II. Ahn, S. J. Ahn, P. B. Griffin, M. W. Hwang, W. S. Lee, S. T. Alm, C. G. Hwang, and M. Y. Lee, "A highly practical modified LOCOS isolation technology for the 256 Mbit DRAM," fEDM Tech. Dig., pp. 679-682, 1994.
-
(1994)
FEDM Tech. Dig.
, pp. 679-682
-
-
Ahn, D.I.I.1
Ahn, S.J.2
Griffin, P.B.3
Hwang, M.W.4
Lee, W.S.5
Alm, S.T.6
Hwang, C.G.7
Lee, M.Y.8
-
13
-
-
0026186149
-
Twin-white-ribbon effect and pit formation mechanism in PBLOCOS
-
T.-H. Lin, N.-S. Tsai, and C.-S. Yoo, "Twin-white-ribbon effect and pit formation mechanism in PBLOCOS," / Electrochem. Soc., vol. 138, no. 7, pp. 2145-2149, 1991.
-
(1991)
Electrochem. Soc.
, vol.138
, Issue.7
, pp. 2145-2149
-
-
Lin, T.-H.1
Tsai, N.-S.2
Yoo, C.-S.3
-
14
-
-
0343018635
-
Transmission electron microscopy charactrization of defects resulting from the polycrystalline silicon buffered local oxidation of silicon isolation process
-
G. A. Dixit, R. L. Hodges, J. W. Staman, F. R. Bryant, R. Sundaresan, C. C. Wsi, and F. T. Liou, "Transmission electron microscopy charactrization of defects resulting from the polycrystalline silicon buffered local oxidation of silicon isolation process," Appl. Phys. Lett. vol. 66, no. 18, pp. 2228-2230, 1992.
-
(1992)
Appl. Phys. Lett.
, vol.66
, Issue.18
, pp. 2228-2230
-
-
Dixit, G.A.1
Hodges, R.L.2
Staman, J.W.3
Bryant, F.R.4
Sundaresan, R.5
Wsi, C.C.6
Liou, F.T.7
-
15
-
-
3943100907
-
Three dimensional improvement of field oxidation by using high pressure oxidation for the gigabit density field isolation
-
S. Deleonibus and S. S. Kim, "Three dimensional improvement of field oxidation by using high pressure oxidation for the gigabit density field isolation," in 1993 SSDM Conference Tech. Digest, 1993, pp. 525-527.
-
1993 SSDM Conference Tech. Digest
, vol.1993
, pp. 525-527
-
-
Deleonibus, S.1
Kim, S.S.2
-
16
-
-
0025522135
-
Reverse L-shape sealed poly-buffer LOCOS technology
-
J. M. Sung, C. Y. Lu, L. B. Fritzinger, T. T. Sheng, and K. H. Lee, "Reverse L-shape sealed poly-buffer LOCOS technology," IEEE Electron Device Lett., vol. 11, no. 11, pp. 549-551, 1990.
-
(1990)
IEEE Electron Device Lett.
, vol.11
, Issue.11
, pp. 549-551
-
-
Sung, J.M.1
Lu, C.Y.2
Fritzinger, L.B.3
Sheng, T.T.4
Lee, K.H.5
-
17
-
-
85067389053
-
A poly-buffer recessed LOCOS process for 256 Mbit DRAM cells
-
N. Shimizu, Y. Naito, Y. Itoh, Y. Shibata, K. Hashimoto, M. Nishio, A. Asai, K. Ohe, H. Umimoto, and Y. Hirofuji, "A poly-buffer recessed LOCOS process for 256 Mbit DRAM cells," 1EDM Tech. Dig., pp. 279-282, 1992.
-
(1992)
1EDM Tech. Dig.
, pp. 279-282
-
-
Shimizu, N.1
Naito, Y.2
Itoh, Y.3
Shibata, Y.4
Hashimoto, K.5
Nishio, M.6
Asai, A.7
Ohe, K.8
Umimoto, H.9
Hirofuji, Y.10
-
18
-
-
0028744296
-
Nitrogen insitu doped poly buffer LOCOS: Simple and scalable isolation technology for deep-submicron silicon devices
-
T. Kobayashi, S. Nakayama, M. Miyake, and Y. Okazaki, "Nitrogen insitu doped poly buffer LOCOS: Simple and scalable isolation technology for deep-submicron silicon devices," IEDM Tech. Dig., pp. 683-686, 1994.
-
(1994)
IEDM Tech. Dig.
, pp. 683-686
-
-
Kobayashi, T.1
Nakayama, S.2
Miyake, M.3
Okazaki, Y.4
-
20
-
-
0026121972
-
Three-dimensional numerical simulation of local oxidation of silicon
-
H. Umimoto and S. Odanaka, "Three-dimensional numerical simulation of local oxidation of silicon," IEEE. Trans. Electron Devices, vol. 38, no. 3, pp. 505-511, 1991.
-
(1991)
IEEE. Trans. Electron Devices
, vol.38
, Issue.3
, pp. 505-511
-
-
Umimoto, H.1
Odanaka, S.2
-
21
-
-
0022199371
-
Stress induced voids in aluminum interconnects during 1C processing
-
J. T. Yue, W. P. Funsten, and R. V. Taylor, "Stress induced voids in aluminum interconnects during 1C processing," in Proc. 1985 IRPS, 1985, pp. 126-135.
-
Proc. 1985 IRPS
, vol.1985
, pp. 126-135
-
-
Yue, J.T.1
Funsten, W.P.2
Taylor, R.V.3
-
22
-
-
0022228065
-
The influence of stress on aluminum conductor life
-
T. Turner and K. Wendel, "The influence of stress on aluminum conductor life," in Proc. 1985 IRPS, 1985, pp. 142-147.
-
Proc. 1985 IRPS
, vol.1985
, pp. 142-147
-
-
Turner, T.1
Wendel, K.2
-
23
-
-
0026979128
-
Characteristics of a new isolated p-vtell structure using thin epitaxy over the buried layer and trench isolation
-
Y. Okazaki, T. Kobayashi, S. Konaka, T. Morimoto, M. Takahashi, K. Imai, and Y. Kado, "Characteristics of a new isolated p-vtell structure using thin epitaxy over the buried layer and trench isolation," IEEE Trans. Electron Devices, vol. 39, no. 12, pp. 2758-2764, 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.12
, pp. 2758-2764
-
-
Okazaki, Y.1
Kobayashi, T.2
Konaka, S.3
Morimoto, T.4
Takahashi, M.5
Imai, K.6
Kado, Y.7
-
24
-
-
0024610567
-
Subqnater-micrometer gatelength p-channel and n-channel MOSFET's with extremely shallow source-drain junctions
-
M. Miyake, T. Kobayasi, and Y. Okazaki, "Subqnater-micrometer gatelength p-channel and n-channel MOSFET's with extremely shallow source-drain junctions," IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 392-398, 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, Issue.2
, pp. 392-398
-
-
Miyake, M.1
Kobayasi, T.2
Okazaki, Y.3
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