A Pipelined 330-MHz Multiplier

IEEE Journal of Solid-State Circuits

Volumn 21, Issue 3, 1986, Pages 411-416

  Noll, Tobias G ^a   Schmitt Landsiedel, Doris ^a   Klar, Heinrich ^a   Enders, Gerhard ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, VLSI - DESIGN; SEMICONDUCTOR DEVICES, MOS - DESIGN; SIGNAL PROCESSING - DIGITAL TECHNIQUES;

PIPELINED MULTIPLIER; SEMISYSTOLIC ARRAY;

COMPUTERS;

EID: 0022736091     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1986.1052543     Document Type: Article

References (7)

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3. J. V. McCanny and J. G. McWhirter, “Completely iterative, pipelined multiplier array suitable for VLSI,” Proc. Inst. Elec. Eng., vol. 129, Pt. G., no. 2, pp. 40–46, Apr. 1982:
4. J. Deverell, “Pipeline iterative arithmetic arrays,” IEEE Trans. Computers, Vol. C-24, pp. 317-322; Mar. 1975.
5. J. R. Jump and S. R. Ahuja, “Effective pipelining of digital systems,” IEEE Trans. Computers; vol. C-27, pp. 855–865, Sept. 1978.
6. R. J. Bayruns et al., “A fine-line nMOS IC raster-scan control of a 500-MHz electron-beam deflection system,” IEEE J. Solid-State Circuits, vol. SC-17, no. 2, pp. 367–374, Apr. 1982.
7. C. A. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison—Wesley, 1980.