A Single Chip Parallel Multiplier by MOS Technology

IEEE Transactions on Computers

Volumn 37, Issue 3, 1988, Pages 274-282

  Nakamura, Shinji ^a   Chu, Kai Yu ^b  

^a DARTMOUTH COLLEGE   (United States)

^b Sun Computers Inc ^*  (United States)

Author keywords

Array multiplier; five counter; partial products; pass gate; squarer

Indexed keywords

LOGIC DESIGN - GATES; SEMICONDUCTOR DEVICES, MOS - DESIGN;

FIVE-COUNTER CELL; FIVE-COUNTER CELL DESIGN; SINGLE CHIP PARALLEL MULTIPLIER; SQUARER;

COMPUTERS, DIGITAL;

EID: 0023965595     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.2164     Document Type: Article

References (10)

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