8 × 8 Bit Pipelined Dadda Multiplier in CMOS

IEE Proceedings G: Electronics Circuits and Systems

Volumn 135, Issue 6, 1988, Pages 231-240

  Crawley, D G ^a   Amaratunga, G A J ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

Very large scale integration

Indexed keywords

COMPUTER AIDED DESIGN; INTEGRATED CIRCUITS, VLSI; LOGIC DESIGN; LOGIC DEVICES; SEMICONDUCTOR DEVICES, MOS;

CMOS PROCESS; DADDA MULTIPLIERS; DADDA SCHEME; PIPELINED PARALLEL MULTIPLIERS;

COMPUTERS;

EID: 0024142020     PISSN: 01437089     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-g-1.1988.0033     Document Type: Article

References (20)

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