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Volumn , Issue , 2000, Pages 451-455

Static timing analysis taking crosstalk into account

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE COUPLING; COUPLING CAPACITANCE; DEEP-SUBMICRON CIRCUITS; GATE DELAYS; LONGEST PATH; SPICE SIMULATIONS; STATIC TIMING ANALYSIS; SYNCHRONOUS CIRCUITS;

EID: 0012078431     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840310     Document Type: Conference Paper
Times cited : (8)

References (11)
  • 2
    • 0028392572 scopus 로고
    • An approach to the analysis and detection of crosstalk faults in digital VLSI circuits
    • A. Rubio, N Itazaki, X. Xu, K. Kinoshita, "An Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits", IEEE T. o. CAD, Vol. 13, No. 3, pp. 387-395, 1994
    • (1994) IEEE T. O. CAD , vol.13 , Issue.3 , pp. 387-395
    • Rubio, A.1    Itazaki, N.2    Xu, X.3    Kinoshita, K.4
  • 3
    • 0030686019 scopus 로고    scopus 로고
    • Calculating worst-case gate delays due to dominant capacitance coupling
    • F. Dartu, L. T. Pileggi, "Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling", Proc. of the 34th ACM/IEEE DAC, pp. 46-51, 1997
    • (1997) Proc. of the 34th ACM/IEEE DAC , pp. 46-51
    • Dartu, F.1    Pileggi, L.T.2
  • 5
    • 27744605313 scopus 로고    scopus 로고
    • A Flat, timing-driven system for a high-performance CMOS processor chipset
    • J. Koehl, U. Baur, T. Ludwig, B. Kick, T. Pflueger, "A Flat, Timing-Driven System for a High-Performance CMOS Processor Chipset", Proc. of the DATE 98, pp. 312-320, 1998
    • (1998) Proc. of the DATE 98 , pp. 312-320
    • Koehl, J.1    Baur, U.2    Ludwig, T.3    Kick, B.4    Pflueger, T.5
  • 6
    • 0031622742 scopus 로고    scopus 로고
    • TETA: Transistor-level engine for timing analysis
    • F. Dartu, L. T. Pileggi, " TETA: Transistor-Level Engine for Timing Analysis", Proc. of the 35th ACM/IEEE DAC, pp. 595-598, 1998
    • (1998) Proc. of the 35th ACM/IEEE DAC , pp. 595-598
    • Dartu, F.1    Pileggi, L.T.2
  • 7
    • 0023386645 scopus 로고
    • Timing analysis and performance improvement of MOS VLSI designs
    • N.P. Jouppi, "Timing Analysis and Performance Improvement of MOS VLSI Designs", IEEE T. o. CAD, Vol. 6, No. 4, pp. 650-665, 1987
    • (1987) IEEE T. O. CAD , vol.6 , Issue.4 , pp. 650-665
    • Jouppi, N.P.1
  • 8
    • 0022953027 scopus 로고
    • LEADOUT: A static timing analyzer for MOS circuits
    • T.G. Szymanski, "LEADOUT: A Static Timing Analyzer for MOS Circuits", ICCAD-86 Digest of Technical Papers, pp. 130-133, 1986
    • (1986) ICCAD-86 Digest of Technical Papers , pp. 130-133
    • Szymanski, T.G.1
  • 10
    • 0000682349 scopus 로고
    • A switch-level timing verifier for digital MOS VLSI
    • J.K. Ousterhout, "A Switch-Level Timing Verifier for Digital MOS VLSI" IEEE T. o. CAD, Vol. 4, No. 3, pp. 336-349, 1985
    • (1985) IEEE T. O. CAD , vol.4 , Issue.3 , pp. 336-349
    • Ousterhout, J.K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.