TETA:Transistor-level engine for timing analysis

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 595-598

  Dartu, Florentin ^a   Pileggi, Lawrence T ^b  

^a INTEL CORPORATION   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FACTORIZATION; MOS DEVICES; NONLINEAR ANALYSIS; TABLE LOOKUP; TIMING CIRCUITS; ALGORITHMS; CAPACITORS; ELECTRIC NETWORK ANALYSIS; ITERATIVE METHODS; MATHEMATICAL MODELS; MATRIX ALGEBRA; NONLINEAR EQUATIONS; OPTIMIZATION; TRANSISTORS; WAVEFORM ANALYSIS;

INTERCONNECT MODELS; MACROMODEL PASSIVITY; MATRIX FACTORIZATIONS; NONLINEAR CAPACITOR; NONLINEAR ITERATIONS; SINGLE INPUT MULTI OUTPUTS; TRANSISTOR LEVEL; WAVEFORM CALCULATOR;

NONLINEAR EQUATIONS; TIMING CIRCUITS;

INTERCONNECT-CENTRIC WAVEFORM CALCULATOR; MATRIX FACTORIZATION; TRANSISTOR-LEVEL ENGINE FOR TIMING ANALYSIS (TETA);

EID: 0031622742     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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