Oxide thickness scaling limit for optimum CMOS logic circuit performance

European Solid-State Device Research Conference

Volumn , Issue , 2000, Pages 300-303

  Bowman, K A ^a   Wang, Lihui ^a   Tang, Xinghai ^b   Meindl, J D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; SOLID STATE DEVICES;

CMOS LOGIC CIRCUITS; DRAIN LEAKAGE; GATE TUNNELING; OXIDE THICKNESS; OXIDE THICKNESS SCALING; SCALING LIMITS;

LOGIC CIRCUITS;

EID: 0004543866     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2000.194774     Document Type: Conference Paper

References (8)

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4. T. Sorsch, et al., "Ultra-thin, 1.0-3.0nm, Gate Oxides for High Performance sub-100nm Technology," 1998 Symp. on VLSI Tech. Dig. of Technical Papers, June 1998, pp. 222-223.
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6. Semiconductor Industry Association, "ITRS," 1999.
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8. B. Yu, et al., "Gate Engineering for Deep-Submicron CMOS Transistors," IEEE Trans. on Ele. Dev., Vol. 45, No. 6, pp. 1253-1262, June 1998.