Sequential equivalence checking by symbolic simulation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1954, Issue , 2000, Pages 423-442

  Ritter, Gerd ^a  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FORMAL METHODS; MODEL CHECKING;

AUTOMATIC VERIFICATION; BEHAVIORAL SPECIFICATION; DEBUGGING SUPPORT; EQUIVALENCE CHECKER; LEVELS OF ABSTRACTION; SEQUENTIAL EQUIVALENCE CHECKING; STATE EXPLOSION PROBLEMS; SYMBOLIC SIMULATION;

EQUIVALENCE CLASSES;

EID: 0004492569     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: None     Document Type: Conference Paper

References (25)

1. M. D. Aagaard, R. B. Jones, and C-J. H. Seger. Combining theorem proving and trajectory evaluation in an industrial environment. In DAC'98, 1998.
2. M. D. Aagaard, R. B. Jones, and C-J. H. Seger. Formal verification using parametric representations of boolean constraints. In DAC'99, 1999.
3. P. Ashar, A. Gupta, and S. Malik. Using complete-1-distinguishability for FSM equivalence checking. In ICCAD'96, 1996.
4. C. W. Barrett, D. L. Dill, and J. R. Levitt. Validity checking for combinations of theories with equality. In FMCAD'96, volume 1166 of LNCS. Springer Verlag, 1996.
5. C. W. Barrett, D. L. Dill, and J. R. Levitt. A decision procedure for bit-vector arithmetic. In DAC'98, 1998.
6. V. Bertacco, M. Damiani, and S. Quer. Cycle-based symbolic simulation of gatelevel synchronous circuits. In DAC'99, 1999.
7. R. E. Bryant. Symbolic verification of MOS circuits. In 1985 Chapel Hill Conference on VLSI, pages 419-438. Computer Science Press, 1985.
8. R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Trans. on Computers, C-35(8): 677-691, 1986.
9. J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In DAC'90, 1990.
10. M. K. Ganai, A. Aziz, and A. Kuehlmann. Enhancing simulation with BDDs and ATPG. In DAC'99, 1999.
11. S. Hazelhurst and C.-J. H. Seger. Symbolic trajectory evaluation. In Formal Hardware Verification, volume 1287 of LNCS. Springer Verlag, 1997.
12. J. L. Hennessy and D. A. Patterson. Computer architecture: a quantitative approach. Morgan Kaufman, CA, second edition, 1996.
13. H. Hinrichsen, H. Eveking, and G. Ritter. Formal synthesis for pipeline design. In DMTCS+CATS'99, Auckland, 1999.
14. S. Höreth. Implementation of a multiple-domain decision diagram package. In CHARME'97, 1997.
15. S. Höreth. Hybrid graph manipulation package demo, Darmstadt, 1998. http://www.rs.e-technik.tu-darmstadt.de/~sth/demo.html.
16. C. N. Ip and D. L. Dill. State reduction using reversible rules. In DAC'96, 1996.
17. R. B. Jones, D. L. Dill, and J. R. Burch. Efficient validity checking for processor verification. In ICCAD'95, 1995.
18. C. Kern and M. R. Greenstreet. Formal hardware verification in hardware design:A survey. ACM Trans. on Design Automation of Electronic Systems, 4(2), 1999.
19. J. O'Leary, X. Zhao, R. Gerth, and C.-J. H. Seger. Formally verifying IEEE compilance of floating-point hardware. Intel Technology Journal, Q1, 1999.
20. M. Pandey and R. E. Bryant. Exploiting symmetry when verifying transistorlevel circuits by symbolic trajectory evaluation. IEEE Trans. on Computer-Aided Design, 18(7): 918-935, 1999.
21. G. Ritter, H. Eveking, and H. Hinrichsen. Formal verification of designs with complex control by symbolic simulation. In CHARME'99, volume 1703 of LNCS. Springer Verlag, 1999.
22. G. Ritter, H. Hinrichsen, and H. Eveking. Formal verification of descriptions with distinct order of memory operations. In ASIAN'99, volume 1742 of LNCS. Springer Verlag, 1999.
23. C.-J. H. Seger and R. E. Bryant. Formal verification by symbolic evaluation of partially-ordered trajectories. Formal Methods in System Design, 6(2): 147-190, 1995.
24. T. Uehara. Proofs and synthesis are cooperative approaches for correct circuit designs. In From HDL Descriptions to Guaranteed Correct Circuit Designs. North-Holland, 1987.
25. L.-C. Wang, M. S. Abadir, and N. Krishnamurthy. Automatic generation of assertions for formal verification of PowerPC™ microprocessor arrays using symbolic trajectory evaluation. In DAC'98, 1998.