Formal verification of descriptions with distinct order of memory operations

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1742, Issue , 1999, Pages 308-321

  Ritter, Gerd ^a   Hinrichsen, Holger ^a   Eveking, Hans ^a  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER AIDED SOFTWARE ENGINEERING; MODEL CHECKING;

COMPLEX CONTROL LOGIC; EQUIVALENCE CHECKER; FORMAL VERIFICATION TOOLS; INDIRECT ADDRESSING; MEMORY OPERATIONS; NEW APPROACHES; SYMBOLIC SIMULATION; TWO PROCESSORS;

FORMAL VERIFICATION;

EID: 84952778181     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46674-6_26     Document Type: Conference Paper

References (14)

1. C. W. Barrett, D. L. Dill, and J. R. Levitt. Validity checking for combinations of theories with equality. In FMCAD'96, volume 1166 of Lecture Notes in Computer Science. Springer Verlag, 1996.
2. C. W. Barrett, D. L. Dill, and J. R. Levitt. A decision procedure for bit-vector arithmetic. In DAC'98, 1998.
3. D. L. Beatty and R. E. Bryant. Formally verifying a microprocessor using a simulation methodology. In DAC'94, 1994.
4. J. R. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential circuit Verification using symbolic model checking. In DAC'90, 1990.
5. J. R. Burch and D. L. Dill. Automatic Verification of pipelined microprocessor control. In CAV'94, volume 818 of Lecture Notes in Computer Science. Springer Verlag, 1994.
6. Digital Equipment Corporation. Alpha architecture handbook, 1992.
7. D. A. Greve. Symbolic simulation of the JEM1 microprocessor. In FMCAD'98, volume 1522 of Lecture Notes in Computer Science. Springer Verlag, 1998.
8. J. L. Hennessy and D. A. Patterson. Computer architecture: a quantitative ap-proach. Morgan Kaufman, CA, second edition, 1996.
9. H. Hinrichsen, H. Eveking, and G. Ritter. Formal synthesis for pipeline design. In DMTCS+CATS'99, Auckland, 1999.
10. Microchip Technology Inc. Microchip data book, 1993.
11. R. B. Jones, D. L. Dill, and J. R. Burch. Efficient validity checking for processor Verification. In ICCAD'95, 1995.
12. J. S. Moore. Symbolic simulation: an ACL2 approach. In FMCAD'98, volume 1522 of Lecture Notes in Computer Science. Springer Verlag, 1998.
13. G. Ritter, H. Eveking, and H. Hinrichsen. Formal Verification of designs with com-plex control by symbolic simulation. In CHARME'99, Lecture Notes in Computer Science. Springer Verlag, 1999.
14. M. N. Velev and R. E. Bryant. Bit-level abstraction in the Verification of pipelined microprocessors by correspondence checking. In FMCAD'98, volume 1522 of Lec-ture Notes in Computer Science. Springer Verlag, 1998.