Lean-power gigascale LSI using hierarchical VBB routing scheme with frequency adaptive VT CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1997, Pages 95-96

  Mizuno, Hiroyuki ^a   Miyazaki, Masayuki ^a   Ishibashi, Koichiro ^a   Nakagome, Yoshinobu ^a   Nagano, Takahiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MOSFET DEVICES; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; SUBSTRATES; TIMING CIRCUITS;

SUBSTRATE BIAS ROUTING; SYSTEM LEVEL INTEGRATION (SLI) DEVICES;

LSI CIRCUITS;

EID: 0031368168     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)