Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 4, 1998, Pages 604-613

  Ruiz, Gustavo A ^a,b  

^a UNIVERSITY OF CANTABRIA   (Spain)

^b UNIVERSITY OF NAVARRA   (Spain)

Author keywords

Adders; Asynchronous addition; Asynchronous design; DCVS logic; Dynamic logic circuit

Indexed keywords

EID: 0000279683     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.663566     Document Type: Article

References (24)

1. T. H. Meng, Synchronization Design for Digital Systems. Boston/Dordrecht/London: Kluwer, 1991.
2. S. Hauck, "Asynchronous design methodologies: An overview," Proc. IEEE, vol. 83, pp. 69-93, Jan. 1995.
3. K. M. Chu and D. L. Pulfrey, "Design procedures for differential cascode voltage switch circuits," IEEE J. Solid-State Circuits, vol. SC-21, pp. 1082-1087, Dec. 1986.
4. _, "A comparison of CMOS circuit techniques: Differential cascode switch logic versus conventional logic," IEEE J. Solid-State Circuits, vol. SC-22, pp. 528-532, Aug. 1987.
5. P. Ng, P. T. Balsara, and D. Steiss, "Performance of CMOS differential circuits," IEEE J. Solid-State Circuits, vol. 31, pp. 841-846, June 1996.
6. N. Kanopoulus, D. Pantzartzis, and F. R. Bartram, "Design of self-checking circuits using DCVS logic: A case study," IEEE Trans. Comput., vol. 41, pp. 891-896, July 1992.
7. G. M. Jacobs and R. W. Brodersen, "A fully asynchronous digital signal processor using self-timed circuits," IEEE J. Solid-State Circuits, vol. 25, pp. 1526-1537, Dec. 1990.
8. J. V. Woods, P. Day, S. B. Further, J. D. Garside, N. C. Paver, and S. Temple, "AMULET1: An asynchronous ARM microprocessor," IEEE Trans. Comput., vol. 46, pp. 385-398, Apr. 1997.
9. R. Ramachandran and S. L. Lu, "Efficient arithmetic using self-timing," IEEE Trans. VLSI Syst., vol. 4, pp. 445-454, Dec. 1996.
10. A. W. Burks, H. H. Goldstine, and J. von Neumann, "Preliminary discussion of the logical design of an electronic computing instrument," in Inst. Advanced Study, Princeton, NJ, June 28, 1947.
11. G. W. Reitwiesner, "The determination of carry propagation length for binary addition," IRE Trans. Electron. Comput., vol. 9, pp. 35-38, Mar. 1960.
12. H. C. Hendrickson, "Fast high-accuracy binary parallel addition," IRE Trans. Electron. Comput., vol. 9, pp. 465-469, Dec. 1960.
13. J. D. Garside, "A CMOS VLSI implementation of an asynchronous ALU," in Proc. IFIP Conf. Asynchronous Design Methodologies, Manchester, England, Apr. 1993, pp. 181-192.
14. M. A. Franklin and T. Pan, "Performance comparation of asynchronous adders," in Proc. Int. Symp. Advanced Res. Asynchronous Circuits and Syst., Salt Lake City, UT, Nov. 1994, pp. 117-125.
15. D. J. Kinniment, "An evaluation of asynchronous addition," IEEE Trans. VLSI Syst., vol. 4, pp. 137-140, Mar. 1996.
16. T. Lynch and E. E. Swartzlander, "A spanning tree carry lookahead adder," IEEE Trans. Comput., vol. 41, pp. 931-939, Aug. 1992.
17. I. S. Hwang and A. L. Fisher, "Ultrafast compact 32-bit CMOS adders in multiple-output domino logic," IEEE J. Solid-State Circuits, vol. 24, pp. 358-369, Apr. 1989.
18. R. P. Brent and H. T. Kung, "A regular layout for parallel adders," IEEE Trans. Comput., vol. C-31, pp. 260-264, Mar. 1982.
19. N. Weste and K. Eshraghian, Principles of CMOS Design: A Systems Perspective. Reading, MA: Addison-Wesley, 1985.
20. G. A. Ruiz, "Compact four bit carry look-ahead CMOS adder in multioutput DCVS logic," Electron. Lett., vol. 32, no. 17, pp. 1556-1557, Aug. 15, 1996.
21. P. K. Chan and M. D. F. Schlag, "Analysis and design of CMOS Manchester adders with variable carry-skip," IEEE Trans. Comput., vol. 39, pp. 983-992, Aug. 1990.
22. T.-Y. Wuu and S. B. K. Vrudhula, "A design of a fast and area efficient multi-input Muller C-element," IEEE Trans. VLSI Syst., vol. 1, pp. 215-219, June 1993.
23. S. L. Lu and M. D. Ercegovac, "Evaluation of two-summand adders implemented in ECDL CMOS differential logic," IEEE J. Solid-State Circuits, vol. 26, pp. 1152-1160, Aug. 1991.
24. M. Renaudin and B. El Hassan, "The design of fast asynchronous adders and their implementation using DCVS logic," in Proc. ISCAS'94, London, UK, May 1994, pp. IV.291-IV.294.