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Volumn 32, Issue 17, 1996, Pages 1556-1557

Compact four bit carry look-ahead CMOS adder in multi-output DCVS logic

Author keywords

CMOS integrated circuits; Logic circuits

Indexed keywords

CASCADE CONNECTIONS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION; LOGIC CIRCUITS; LOGIC GATES; SWITCHING CIRCUITS; TRANSISTORS;

EID: 0030212104     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19961082     Document Type: Article
Times cited : (7)

References (3)
  • 1
    • 0022867125 scopus 로고
    • Design procedures for Differential Cascode Voltage Switch Circuits
    • CHU, LK.M., and PUFFREY, D.L.: 'Design procedures for Differential Cascode Voltage Switch Circuits', IEEE J. Solid-Slate Circuits, 1986, 21, (6), pp. 1082-1087
    • (1986) IEEE J. Solid-Slate Circuits , vol.21 , Issue.6 , pp. 1082-1087
    • Chu, L.K.M.1    Puffrey, D.L.2
  • 3
    • 0024647831 scopus 로고
    • Ultrafast compact 32-bit CMOS adders in multiple-output domino logic
    • HWANG, I.S., and FISHER, A.L.: 'Ultrafast compact 32-bit CMOS adders in multiple-output domino logic', IEEE J. Solid-State Circuits, 1989, 24, (2), pp. 358-369
    • (1989) IEEE J. Solid-State Circuits , vol.24 , Issue.2 , pp. 358-369
    • Hwang, I.S.1    Fisher, A.L.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.