Efficient arithmetic using self-timing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 4, Issue 4, 1996, Pages 445-454

  Ramachandran, Ravi ^a   Lu, Shih Lien ^b  

^a AGERE SYSTEMS   (United States)

^b OREGON STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; DIGITAL ARITHMETIC; INTERFACES (COMPUTER); TIMING CIRCUITS; VLSI CIRCUITS;

CARRY ELIMINATION ADDERS; SELF TIMING; SKEW MINIMIZATION;

ADDERS;

EID: 0030421823     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.544409     Document Type: Article

References (16)

1. I. Koren, Computer Arithmetic Algorithms. Englewood Cliffs, NJ: Prentice-Hall, 1993, ch. 5, pp. 71-92.
2. K. Hwang, Computer Arithmetic. New York: Wiley, 1979, ch. 3, pp. 69-93.
3. N. Weste and K. Eshragian, Principles of VLSI Design. Reading, MA: Addison-Wesley, 1985.
4. B. W. Y Wei and C. D. Thompson, "Area-time optimal adder design," IEEE Trans. Comput., vol. 39, May 1990.
5. R. Ramachandran and S.-L. Lu, "An efficient selftimed adder design," in Proc: IEEE Int. ASIC Conf., Sept. 1995, pp. 303-306.
6. I. E. Sutherland, "Micropipelines," Commun. ACM, vol. 32 no. 6, pp. 720-738, June 1989.
7. S.-L. Lu and M. Ercegovac, "A novel CMOS implementation of double-edge-triggered-flip-flops," IEEE J. Solid State Circuits, vol. 25, pp. 1008-1010, Aug. 1990.
8. R. Ramachandran, "Efficient arithmetic using self-timing," Master's thesis, Dep. Elec. Comput. Eng., Oregon State Univ., ch. 3, Sept. 1994.
9. A. Burks, H. H. Goldstine, and J. Von Neumann, "Preliminary discussion of logic design of an electronic computing instrument," Inst. Advanced Study, Princeton, NJ, 1946.
10. R. Ramachandran, S. Agrawal, V. Amla, R. Landy, G. Mahadevan, and Z. Sarkari, "System on a chip design verification," in Super DesignCon'96, Feb. 1996.
11. R. Ramachandran, "Efficient arithmetic using self-timing," Master's thesis, Dep. Elec. Comput. Eng., Oregon State Univ., ch. 5, Sept. 1994.
12. MOTIVE Reference Manual, Quad Design Technology, 1993.
13. PowerView Reference Manual, Viewlogic, 1994.
14. J. Sklansky, "An evaluation of several two-summand binary adders," vol. EC-9, no. 2, pp. 226-231, June 1960.
15. R. Ramachandran, "Efficient arithmetic using self-timing," Master's thesis, Dep. Elec. Comput. Eng., Oregon State Univ., ch. 4, Sept. 1994.
16. O. Bair et al., "System design environment with pre-designed cores," in Proc. IEEE Int. ASIC Conf., Sept. 1995, pp. 378-381.