Generating compact, guaranteed passive reduced-order models of 3-D RLC interconnects

IEEE Transactions on Advanced Packaging

Volumn 27, Issue 4, 2004, Pages 569-580

  Marques, Nuno Alexandre ^a   Kamon, Mattan ^b   Silveira, Luís Miguel ^c,d   White, Jacob K ^e  

^a Department of Mobile Communications   (Portugal)

^b European Headquarter and Development Center   (United States)

^c INESC ID   (Portugal)

^d CADENCE DESIGN SYSTEMS   (United States)

^e MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Computational electromagnetics; Coupled circuit interconnect simulation; Interconnect modeling; Krylov subspace; Model order reduction; Packaging analysis; Truncated balanced realization

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; COUPLED CIRCUITS; ELECTRIC CONDUCTORS; ELECTRIC CURRENTS; ELECTRIC IMPEDANCE; ELECTROMAGNETIC FIELD EFFECTS; EQUIVALENT CIRCUITS; FREQUENCY DOMAIN ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; TIME DOMAIN ANALYSIS;

COMPUTATIONAL ELECTROMAGNETICS; COUPLED CIRCUIT INTERCONNECT SIMULATION; INTERCONNECT MODELING; KRYLOV SUBSPACE; MODEL ORDER REDUCTION; PACKAGING ANALYSIS; TRUNCATED BALANCED REALIZATION;

CHIP SCALE PACKAGES;

EID: 9244256783     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2004.831867     Document Type: Article

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