A method for reduced-order modeling and simulation of large interconnect circuits and its application to PEEC models with retardation

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 4, 2000, Pages 261-273

  Cullum, Jane ^a   Ruehli, Albert ^b   Zhang, Tong ^a  

^a TJ Watson Research Center ^*  (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Arnoldi; Electronic interconnect package (eip); Interconnect circuits; Iterative methods; Lanczos; Mimo systems; Model reduction; Peec systems; Reduced models; Reduced order systems; Time delays; Transfer function

Indexed keywords

EID: 0000953807     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.839662     Document Type: Article

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