An efficient algorithm for fast parasitic extraction and passive order reduction of 3D interconnect models

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 538-543

  Marques, Nuno ^a   Kamon, Mattan ^b   White, Jacob ^b   Silveira, L Miguel ^a  

^a INSTITUTO SUPERIOR TÉCNICO   (Portugal)

^b USA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE ACCUMULATION; CIRCUIT SIMULATORS; INTEGRAL EQUATION APPROACHES; INTERCONNECT MODELS; INTERCONNECT STRUCTURES; MODIFIED NODAL ANALYSIS; ORDER REDUCTION; PARASITIC EXTRACTION;

ALGORITHMS; VLSI CIRCUITS;

THREE DIMENSIONAL;

EID: 84893769776     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655910     Document Type: Conference Paper

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