Low power implementation of a turbo-decoder on programmable architectures

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 400-403

  Gilbert, F ^a   Worm, A ^a   Wehn, N ^a  

^a Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

Author keywords

Bit error rate; Channel coding; Dynamic voltage scaling; Error correction; Forward error correction; Iterative decoding; Processor scheduling; Redundancy; Signal processing algorithms; Turbo codes

Indexed keywords

BIT ERROR RATE; CHANNEL CODING; COMPUTER AIDED DESIGN; DECODING; ENERGY UTILIZATION; ERROR CORRECTION; ERRORS; FORWARD ERROR CORRECTION; HARDWARE; ITERATIVE METHODS; MEMORY ARCHITECTURE; MOBILE RADIO SYSTEMS; OPTICAL COMMUNICATION; OPTIMIZATION; REDUNDANCY; SCHEDULING; SIGNAL PROCESSING; TURBO CODES; VOLTAGE SCALING; VOLTAGE STABILIZING CIRCUITS;

CANCELLATION TECHNIQUES; HARDWARE IMPLEMENTATIONS; LOW POWER IMPLEMENTATION; LOW-POWER OPTIMIZATIONS; PROCESSOR SCHEDULING; PROGRAMMABLE ARCHITECTURES; SIGNAL PROCESSING ALGORITHMS; VOLTAGE SCHEDULING;

ITERATIVE DECODING;

EID: 84949796242     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913340     Document Type: Conference Paper

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