An evaluation of network stack parallelization strategies in modern operating systems

USENIX 2006 Annual Technical Conference

Volumn , Issue , 2006, Pages 91-96

  Willmann, Paul ^a   Rixner, Scott ^a   Cox, Alan L ^a  

^a RICE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPROCESSING SYSTEMS;

CHIP MULTIPROCESSOR; CONCURRENT PROCESSING; CONCURRENT THREADS; HANDOFF MECHANISMS; NETWORK OPERATIONS; PARALLELIZATION STRATEGIES; THROUGHPUT IMPROVEMENT; UNIPROCESSOR KERNELS;

LOCKS (FASTENERS);

EID: 85077343390     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. BJÖRKMAN, M., AND GUNNINGBERG, P. Performance modeling of multiprocessor implementations of protocols. IEEE/ACM Transactions on Networking (June 1998).
2. DIEFENDORFF, K. Power4 focuses on memory bandwidth. Microprocessor Report (Oct. 1999).
3. HURWITZ, J., AND FENG, W. End-to-end performance of 10-gigabit Ethernet on commodity systems. IEEE Micro (Jan./Feb. 2004).
4. KAPIL, S., MCGHAN, H., AND LAWRENDRA, J. A chip multithreaded processor for network-facing workloads. IEEE Micro (Mar./Apr. 2004).
5. KIM, H., AND RIXNER, S. Performance characterization of the FreeBSD network stack. Tech. Rep. TR05-450, Rice University Computer Science Department, June 2005.
6. KIM, H., AND RIXNER, S. TCP offload through connection handoff. In Proceedings of EuroSys (Apr. 2006).
7. KONGETIRA, P., AINGARAN, K., AND OLUKOTUN, K. Niagara: A 32-way multithreaded SPARC processor. IEEE Micro (Mar./Apr. 2005).
8. KREWELL, K. UltraSPARC IV mirrors predecessor. Microprocessor Report (Nov. 2003).
9. KREWELL, K. Double your Opterons; double your fun. Microprocessor Report (Oct. 2004).
10. KREWELL, K. Sun’s Niagara pours on the cores. Microprocessor Report (Sept. 2004).
11. NAHUM, E. M., YATES, D. J., KUROSE, J. F., AND TOWSLEY, D. Performance issues in parallelized network protocols. In Proceedings of the Symposium on Operating Systems Design and Implementation (Nov. 1994).
12. OLUKOTUN, K., NAYFEH, B. A., HAMMOND, L., WILSON, K., AND CHANG, K. The case for a single-chip multiprocessor. In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems (Oct. 1996).
13. ROCA, V., BRAUN, T., AND DIOT, C. Demultiplexed architectures: A solution for efficient STREAMS-based communication stacks. IEEE Network (July 1997).
14. SCHMIDT, D. C., AND SUDA, T. Measuring the performance of parallel message-based process architectures. In Proceedings of the INFOCOM Conference on Computer Communications (Apr. 1995).
15. TENDLER, J. M., DODSON, J. S., J. S. FIELDS, J., LE, H., AND SINHAROY, B. Power4 system architecture. IBM Journal of Research and Development (Jan. 2002).
16. TRIPATHI, S. FireEngine—a new networking architecture for the Solaris operating system. White paper, Sun Microsystems, June 2004.
17. WILLMANN, P., RIXNER, S., AND COX, A. L. An evaluation of network stack parallelization strategies in modern operating systems. Tech. Rep. TR06-872, Rice University Computer Science Department, Apr. 2006.
18. YATES, D. J., NAHUM, E. M., KUROSE, J. F., AND TOWSLEY, D. Networking support for large scale multiprocessor servers. In Proceedings of the 1996 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (May 1996).