-
1
-
-
84880861455
-
Preemptively scheduling hard-real-time sporadic tasks on one processor
-
Sanjoy K Baruah, Aloysius K Mok, and Louis E Rosier. Preemptively scheduling hard-real-time sporadic tasks on one processor. In Proc. of IEEE RTSS, 1990.
-
(1990)
Proc. of IEEE RTSS
-
-
Baruah, S.K.1
Mok, A.K.2
Rosier, L.E.3
-
2
-
-
84872382711
-
Programming heterogeneous many-core platforms in nanometer technology: The p2012 experience
-
Luca Benini. Programming heterogeneous many-core platforms in nanometer technology: The p2012 experience. Presentation in the ARTIST Summer School, 2010.
-
(2010)
Presentation in the ARTIST Summer School
-
-
Benini, L.1
-
3
-
-
24944507809
-
Measuring the performance of schedulability tests
-
Enrico Bini and Giorgio C Buttazzo. Measuring the performance of schedulability tests. Real Time Systems, 30(1-2):129-154, 2005.
-
(2005)
Real Time Systems
, vol.30
, Issue.1-2
, pp. 129-154
-
-
Bini, E.1
Buttazzo, G.C.2
-
4
-
-
84921407763
-
Real-time task scheduling on island-based multi-core platforms
-
Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo, and Heiko Falk. Real-time task scheduling on island-based multi-core platforms. IEEE TPDS, 26(2):538-550, 2015.
-
(2015)
IEEE TPDS
, vol.26
, Issue.2
, pp. 538-550
-
-
Chang, C.-W.1
Chen, J.-J.2
Kuo, T.-W.3
Falk, H.4
-
5
-
-
84894307471
-
Task set synthesis with cost minimization for sporadic real-time tasks
-
Jian-Jia Chen. Task set synthesis with cost minimization for sporadic real-time tasks. In Proc. of IEEE RTSS, 2013.
-
(2013)
Proc. of IEEE RTSS
-
-
Chen, J.-J.1
-
6
-
-
84987927704
-
Many-core real-time task scheduling with scratchpad memory
-
Sheng-Wei Cheng, Che-Wei Chang, Jian-Jia Chen, Tei-Wei Kuo, and Pi-Cheng Hsiu. Many-core real-time task scheduling with scratchpad memory. IEEE TPDS, 27(10):2953-2966, 2016.
-
(2016)
IEEE TPDS
, vol.27
, Issue.10
, pp. 2953-2966
-
-
Cheng, S.-W.1
Chang, C.-W.2
Chen, J.-J.3
Kuo, T.-W.4
Hsiu, P.-C.5
-
7
-
-
49149111959
-
Efficient exact schedulability tests for fixed priority real-time systems
-
Robert I Davis, Attila Zabos, and Alan Burns. Efficient exact schedulability tests for fixed priority real-time systems. IEEE TC, 57(9):1261-1276, 2008.
-
(2008)
IEEE TC
, vol.57
, Issue.9
, pp. 1261-1276
-
-
Davis, R.I.1
Zabos, A.2
Burns, A.3
-
8
-
-
85172637180
-
-
B. D. de Dinechin, R. Ayrignac, P. E. Beaucamps, P. Couvert, B. Ganne, P. G. de Massas, F. Jacquet, S. Jones, N. M. Chaisemartin, F. Riss, and T. Strudel. In Proc. of IEEE HPEC, 2013.
-
(2013)
Proc. of IEEE HPEC
-
-
De Dinechin, B.D.1
Ayrignac, R.2
Beaucamps, P.E.3
Couvert, P.4
Ganne, B.5
De Massas, P.G.6
Jacquet, F.7
Jones, S.8
Chaisemartin, N.M.9
Riss, F.10
Strudel, T.11
-
11
-
-
84938539728
-
Towards compositionality in execution time analysis: Definition and challenges
-
Sebastian Hahn, Jan Reineke, and Reinhard Wilhelm. Towards compositionality in execution time analysis: Definition and challenges. ACM SIGBED Review, 12(1):28-36, 2015.
-
(2015)
ACM SIGBED Review
, vol.12
, Issue.1
, pp. 28-36
-
-
Hahn, S.1
Reineke, J.2
Wilhelm, R.3
-
12
-
-
84977098176
-
Mirror: Symmetric timing analysis for real-time tasks on multicore platforms with shared resources
-
Wen-Hung Huang, Jian-Jia Chen, and Jan Reineke. Mirror: Symmetric timing analysis for real-time tasks on multicore platforms with shared resources. In Proc. of ACM DAC, 2016.
-
(2016)
Proc. of ACM DAC
-
-
Huang, W.-H.1
Chen, J.-J.2
Reineke, J.3
-
13
-
-
52049125736
-
-
Morgan Kaufmann
-
Bruce Jacob, Spencer Ng, and David Wang. Memory systems: Cache, DRAM, disk. Morgan Kaufmann, 2010.
-
(2010)
Memory Systems: Cache, DRAM, Disk
-
-
Jacob, B.1
Ng, S.2
Wang, D.3
-
14
-
-
0000696568
-
Speed is as powerful as clairvoyance
-
Bala Kalyanasundaram and Kirk Pruhs. Speed is as powerful as clairvoyance. Journal of the ACM, 47(4):617-643, 2000.
-
(2000)
Journal of the ACM
, vol.47
, Issue.4
, pp. 617-643
-
-
Kalyanasundaram, B.1
Pruhs, K.2
-
15
-
-
84959176441
-
Bounding and reducing memory interference in cots-based multi-core systems
-
Hyoseung Kim, Dionisio De Niz, Björn Andersson, Mark Klein, Onur Mutlu, and Ragunathan Rajkumar. Bounding and reducing memory interference in cots-based multi-core systems. Real-Time Systems, 52(3):356-395, 2016.
-
(2016)
Real-Time Systems
, vol.52
, Issue.3
, pp. 356-395
-
-
Kim, H.1
De Niz, D.2
Andersson, B.3
Klein, M.4
Mutlu, O.5
Rajkumar, R.6
-
16
-
-
27544456315
-
-
Rakesh Kumar, Victor Zyuban, and Dean M Tullsen. Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling. 33(2):408-419, 2005.
-
(2005)
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
, vol.33
, Issue.2
, pp. 408-419
-
-
Kumar, R.1
Zyuban, V.2
Tullsen, D.M.3
-
17
-
-
84959502239
-
Memoryprocessor co-scheduling in fixed priority systems
-
Alessandra Melani, Marko Bertogna, Vincenzo Bonifaci, Alberto Marchetti-Spaccamela, and Giorgio Buttazzo. Memoryprocessor co-scheduling in fixed priority systems. In Proceedings of ACM RTNS, 2015.
-
(2015)
Proceedings of ACM RTNS
-
-
Melani, A.1
Bertogna, M.2
Bonifaci, V.3
Marchetti-Spaccamela, A.4
Buttazzo, G.5
-
18
-
-
84997350106
-
The variability of application execution times on a multi-core platform
-
Vincent Nélis, Patrick Meumeu Yomsi, and Luís Miguel Pinho. The Variability of Application Execution Times on a Multi-Core Platform. In Proc. of WCET, 2016.
-
(2016)
Proc. of WCET
-
-
Nélis, V.1
Yomsi, P.M.2
Pinho, L.M.3
-
19
-
-
77953092559
-
Worst case delay analysis for memory interference in multicore systems
-
Rodolfo Pellizzoni, Andreas Schranzhofer, Jian-Jia Chen, Marco Caccamo, and Lothar Thiele. Worst case delay analysis for memory interference in multicore systems. In Proc. of IEEE DATE, 2010.
-
(2010)
Proc. of IEEE DATE
-
-
Pellizzoni, R.1
Schranzhofer, A.2
Chen, J.-J.3
Caccamo, M.4
Thiele, L.5
-
21
-
-
67650862807
-
Memory hierarchies, pipelines, and buses for future architectures in timecritical embedded systems
-
Reinhard Wilhelm, Daniel Grund, Jan Reineke, Marc Schlickling, Markus Pister, and Christian Ferdinand. Memory hierarchies, pipelines, and buses for future architectures in timecritical embedded systems. IEEE TCAD, 28(7):966, 2009.
-
(2009)
IEEE TCAD
, vol.28
, Issue.7
, pp. 966
-
-
Wilhelm, R.1
Grund, D.2
Reineke, J.3
Schlickling, M.4
Pister, M.5
Ferdinand, C.6
|