-
1
-
-
33847658333
-
High Speed Word-Parallel Bit-Serial Normal Basis Finite Field Multiplier and Its FPGA Implementation
-
Nov
-
A.H. Namin, H. Wu, and M. Ahmadi, "High Speed Word-Parallel Bit-Serial Normal Basis Finite Field Multiplier and Its FPGA Implementation," Proc. 39th Asilomar Conf. Signals, Systems, and Computers, pp. 1338-1341, Nov. 2005.
-
(2005)
Proc. 39th Asilomar Conf. Signals, Systems, and Computers
, pp. 1338-1341
-
-
Namin, A.H.1
Wu, H.2
Ahmadi, M.3
-
2
-
-
0020207091
-
Bit-Serial Reed-Solomon Encoders
-
E.R. Berlekamp, "Bit-Serial Reed-Solomon Encoders," IEEE Trans. Information Theory, vol. 28, pp. 869-974, 1982.
-
(1982)
IEEE Trans. Information Theory
, vol.28
, pp. 869-974
-
-
Berlekamp, E.R.1
-
3
-
-
0000895310
-
m Yielding Small Complexity Arithmetic Circuits
-
Sept
-
m Yielding Small Complexity Arithmetic Circuits," IEEE Trans. Computers, vol. 47, no. 9, pp. 938-946, Sept. 1998.
-
(1998)
IEEE Trans. Computers
, vol.47
, Issue.9
, pp. 938-946
-
-
Drolet, G.1
-
4
-
-
84968467386
-
On Order of Optimal Normal Basis Generators
-
S. Gao and S. Vanstone, "On Order of Optimal Normal Basis Generators," Math. Computation, vol. 64, no. 2, pp. 1227-1233, 1995.
-
(1995)
Math. Computation
, vol.64
, Issue.2
, pp. 1227-1233
-
-
Gao, S.1
Vanstone, S.2
-
6
-
-
0027115438
-
m)
-
8 Oct
-
m)," Electronics Letters, vol. 28, no. 21, pp. 1984-1986, 8 Oct. 1992.
-
(1992)
Electronics Letters
, vol.28
, Issue.21
, pp. 1984-1986
-
-
Hasan, M.A.1
Bhargava, V.K.2
-
7
-
-
0038639373
-
Low Complexity Multiplication in a Finite Field Using Ring Representation
-
Apr
-
R. Katti and J. Brennan, "Low Complexity Multiplication in a Finite Field Using Ring Representation," IEEE Trans. Computers, vol. 52, no. 4, pp. 418-427, Apr. 2003.
-
(2003)
IEEE Trans. Computers
, vol.52
, Issue.4
, pp. 418-427
-
-
Katti, R.1
Brennan, J.2
-
9
-
-
0004216195
-
Computational Method and Apparatus for Finite Field Arithmetic,
-
US patent application
-
J.L. Massey and J.K. Omura, "Computational Method and Apparatus for Finite Field Arithmetic," US patent application, 1984.
-
(1984)
-
-
Massey, J.L.1
Omura, J.K.2
-
10
-
-
0003393443
-
VLSI Architectures for Computations in Galois Fields,
-
PhD dissertation, Linköping Univ, Linköping, Sweden
-
E.D. Mastrovito, "VLSI Architectures for Computations in Galois Fields," PhD dissertation, Linköping Univ., Linköping, Sweden, 1991.
-
(1991)
-
-
Mastrovito, E.D.1
-
11
-
-
0022108239
-
m)
-
Aug
-
m)," IEEE Trans. Computers, vol. 34, no. 8, pp. 709-717, Aug. 1985.
-
(1985)
IEEE Trans. Computers
, vol.34
, Issue.8
, pp. 709-717
-
-
Wang, C.C.1
Truong, T.K.2
Shao, H.M.3
Deutsch, L.J.4
Omura, J.K.5
Reed, I.S.6
-
12
-
-
0036859286
-
Finite Field Multiplier Using Redundant Representation
-
Nov
-
H. Wu, M.A. Hasan, I.F. Blake, and S. Gao, "Finite Field Multiplier Using Redundant Representation," IEEE Trans. Computers, vol. 51, no. 11, pp. 1306-1316, Nov. 2002.
-
(2002)
IEEE Trans. Computers
, vol.51
, Issue.11
, pp. 1306-1316
-
-
Wu, H.1
Hasan, M.A.2
Blake, I.F.3
Gao, S.4
-
13
-
-
0038639375
-
m)
-
special issue on embedded systems and security, Apr
-
m)," ACM Trans. Embedded Computing Systems, special issue on embedded systems and security, vol. 52, no. 4, pp. 428-439, Apr. 2003.
-
(2003)
ACM Trans. Embedded Computing Systems
, vol.52
, Issue.4
, pp. 428-439
-
-
Reyhani-Masoleh, A.1
Hasan, M.A.2
-
14
-
-
14844353746
-
Low Complexity Word-Level Sequential Normal Basis Multipliers
-
Feb
-
A. Reyhani-Masoleh and M.A. Hasan, "Low Complexity Word-Level Sequential Normal Basis Multipliers," IEEE Trans. Computers, vol. 54, no. 2, pp. 98-110, Feb. 2005.
-
(2005)
IEEE Trans. Computers
, vol.54
, Issue.2
, pp. 98-110
-
-
Reyhani-Masoleh, A.1
Hasan, M.A.2
-
15
-
-
34547914260
-
-
Stratix Architecture, Stratix Device Handbook, version 3.3, chapter 2, Altera Corp, July 2005
-
"Stratix Architecture," Stratix Device Handbook, version 3.3, chapter 2, Altera Corp., July 2005.
-
-
-
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