Quantifying the value of ownership of yield analysis technologies

10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, ASMC 1999

Volumn , Issue , 1999, Pages 64-70

  Weber, C ^a   Sankaran, V ^b   Scher, G ^c   Tobin, K W ^d  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b SEMATECH   (United States)

^c Sleuthworks Inc   (United States)

^d OAK RIDGE NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EXTRACTION; INFORMATION THEORY; MANUFACTURE; SEMICONDUCTOR DEVICE MANUFACTURE;

AUTOMATIC DEFECT CLASSIFICATION; BENCHMARKING METRICS; ELECTRICAL TESTING; KNOWLEDGE EXTRACTION; OPTIMAL PORTFOLIOS; POSITION ANALYSIS; SPATIAL SIGNATURE; YIELD ANALYSIS TOOLS;

MANAGERS;

EID: 85015113811     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.1999.798183     Document Type: Conference Paper

References (27)

1. R. Leckie, "A model for analyzing test capacity, cost and productivity, " IEEE International Test Conference, 1986 pp. 213-218
2. R. Martinez, V. Czitrom, N pierce and S. Srodes, "A methodology for optimizing Cost of Ownership, " SPIE Vol. 1803 (1992) pp. 363-387
3. J. Secrest and P. Burggraaf, "The reasoning behind Cost of Ownership, " Semiconductor International, May 1993
4. D. Dance and D. Jimenez, "Applications of Cost of Ownership, " Semiconductor International, Sept. 1994, pp. 6-7
5. L. Chao, D. Dance and T. DiFloria, "Get a handle on your cost of test, " Test and Measurement World, April 1995, pp. 45-50
6. Wang E., Holtan M.Akella R.,Emami I.,McLntyre M.,Jensen D.,Fletcher D. Valuation of yield management investments, Proc IEEE/SEMYASMC, Cambridge, Mass, 1997, 1-7
7. E. Wang, M. Holtan, R. Akella, I. Emami, M. Mclntyre, D. Jensen and D. Fletcher, "Valuation of Yield Management Investments, " Proc IEEE/SEMYASMC, Cambridge, Mass., 1997, pp. 1-7 P. Silverman, "Capital Productivity: Major Challenge for the Semiconductor Industry, " Solid State Technology, Vol. 37, No. 3, p 104, March 1994
8. C. Weber, D. Jensen and E. D. Hirleman, "What drives defect detection technology?" Micro, June 1998, pp. 51-72
9. C. Stapper and R. Rosner, "Integrated circuit yield management and yield analysis: Development and Implementation, " IEEE Trans Semicond. Manufact., Vol. 8, no. 2, pp. 95-101, May 1995
10. C. Weber, B. Moslehi and M. Dutta, "An integrated framework for yield management and defect/fault reduction, " IEEE Trans. Semicond Manufact., Vol. 8, no. 2, pp. 110-120, May 1995
11. M. Iansiti and J. West, "Technology Integration, " Harvard Business Review, May-June 1997, pp. 69-79
12. D. Jensen, C. Gross and D. Mehta, "New industry document explores defect reduction technology challenges, " Micro, January 1998, pp.35-, 44
13. C Weber, "Accelerating Three-Dimensional Experience Curves in Integrated Circuit Process Development, " MIT May, 1996, (Management of Technology Masters Thesis)
14. S H. Thomke, Managing experimentation in the design of new products, Management ScienceNol, 44, 6, 743-762, June 1998
15. V. Sankaran, C. Weber, K. W. Tobin, and F. Lakhani, "Inspection in Semiconductor Manufacturing, " Websters Encyclopedia of Electrical and Electronics, Volume 10 (Pattern Analysis and Machine Intelligence), pp. 242-262, Wiley & Sons, NY, NY, 1999
16. C. E. Shannon and W. Weaver, The Mathematical Theory of Communication, (Urbana: University of Illinois Press, 1949) N. Abrarnson, Information Theory and Coding, (New York: McGraw-Hill, 1963)
17. P. Beckmann, Probability in Communication Engineering, (New York: Harcourt, Brace & World, Inc., 1967)
18. T. M. Cover, and J. A. Thomas, Elements of Information Theory, (New York: Wiley, 1991)
19. R V. L. Hartley, Transmission of Information, " Bell System Tech. J., S. Kullback, Information Theory and Statistics, New York Dover 1968
20. C. Ncorn, D. Dworak, N. Haddad, W. Henley and P. Nixon, "Kerf test structure designs for process and device characterization, " Solid State Technology, May 1985, pp. 229-235
21. G. Scher, D. Eaton, J. Sorensen, B. Femelius and J. Akers, "In-line statistical process control and feedback for VLSI integrated circuit manufacturing, " IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 13, No. 3, pp. 484-489, September 1990
22. G. Scher, "Wafer tracking comes of age, " Semiconductor International, pp. 126-131, May 1991
23. C. Weber, " A standardized method for CMOS unit process development, " IEEE Trans. Semicond. Manufact., Vol. 5, no. 2 94-100, May 1992
24. M. H. Bennett, K. W. Tobin, and S. S. Gleason, "Automatic Defect Classification: Status and Industry Trends, " SPIE Metrology, Inspection, and Process Control for Microlithography M, Vol. 2439, p 210, San Jose, CA, March 1995
25. K. W. Tobin, S. S. Gleason, F. Lakhani, and M. H. Bennett, "Automated Analysis for Rapid Defect Sourcing and Yield Learning", Future Fab International, Issue 4, Vol. 1, Technology Publishing Ltd., London 1997, p. 313
26. S. S Gleason, K. W. Tobin, T. P. Kamowskim An Integrated Spatial Signature Analysis and Automatic Defect Classification System 19lst Meeting of the Electrochemical Society, Inc May
27. A. Shapiro, T. James and B. Trafas, "Advanced inspection for 0.25-um-generation semiconductor manufacturing, " SPIEs 22nd Annual