DLAU: A scalable deep learning accelerator unit on FPGA

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 36, Issue 3, 2017, Pages 513-517

  Wang, Chao ^a   Gong, Lei ^a   Yu, Qi ^a   Li, Xi ^a   Xie, Yuan ^b   Zhou, Xuehai ^a  

^a UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Deep learning; field programmable gate array (FPGA); hardware accelerator; neural network

Indexed keywords

ACCELERATION; COMPLEX NETWORKS; DEEP NEURAL NETWORKS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; LEARNING SYSTEMS; LOGIC GATES; LOW POWER ELECTRONICS; NEURAL NETWORKS; PIPELINE PROCESSING SYSTEMS;

ACCELERATOR ARCHITECTURES; COMPLEX LEARNING; HARDWARE ACCELERATORS; HARDWARE PROTOTYPE; HIGH PERFORMANCE IMPLEMENTATIONS; LEARNING NETWORK; LEARNING NEURAL NETWORKS; PIPELINED PROCESSING;

DEEP LEARNING;

EID: 85013628943     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2016.2587683     Document Type: Article

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