A high-performance FPGA architecture for restricted machines

Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'09

Volumn , Issue , 2009, Pages 73-82

  Ly, Daniel L ^a   Chow, Paul ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

Design; Neural network hardware; Performance; Restricted Boltzmann machines

Indexed keywords

C PROGRAMS; COMPUTATIONAL SPEED; FPGA ARCHITECTURES; GENERAL PURPOSE PROCESSORS; HARDWARE FRAMEWORK; INHERENT PARALLELISM; INTEL PROCESSORS; MULTI-PURPOSE; NEURAL NETWORK HARDWARE; PERFORMANCE; RESTRICTED BOLTZMANN MACHINES; SPEED-UP;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GENERAL PURPOSE COMPUTERS; INDUSTRIAL APPLICATIONS; LOGIC GATES; MACHINE DESIGN; PROGRAM PROCESSORS; SCALABILITY;

NEURAL NETWORKS;

EID: 67650661629     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508128.1508140     Document Type: Conference Paper

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