Resource-efficient FPGA architecture of canny edge detector

ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Volumn , Issue , 2016, Pages 299-300

  Jang, Yunseok ^a   Mun, Junwon ^a   Kim, Jaeseok ^a  

^a Yonsei University   (South Korea)

Author keywords

Canny edge detection; FPGA architecture; Real time

Indexed keywords

EDGE DETECTION; FEATURE EXTRACTION; IMAGE PROCESSING;

CANNY EDGE DETECTION; CANNY EDGE DETECTORS; EDGE DETECTORS; FPGA ARCHITECTURES; HARDWARE ARCHITECTURE; IMAGE SMOOTHING; REAL TIME; RESOURCE-EFFICIENT;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 85010310966     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISOCC.2016.7799796     Document Type: Conference Paper

References (4)

1. Canny J, "A Computational Approach to Edge Detection" IEEE Trans. Pattern Anal. Mach. Intell. vol. 8, no. 6, pp. 679-698, NOV. 1986.
2. Wenhao H, Kui.Y "An improved Canny edge detector and its realization on FPGA" World Congress on Intelligent Control and Automation pp. 6561-6564, JUN. 2008.
3. Gentsos. C, Sotiropoulou. C. L "Real-Time Canny edge detection parallel implementation for FPGAs" IEEE Int. Conf. Electronics, Circuits, and Systems. pp. 499-502, DEC. 2010.
4. Xiaoyang. L, Jie. J, Qiaoyun. F "An improved Real-Time Hardware Architecture for Canny Edge Detection Based on FPGA" International Conference on Intelligent Control and Information Processing pp. 445- 449, JULY. 2012.